linux-kernel - Re: Support for configurable PCIe endpoint

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Message-ID: <57C420C4.4000004@ti.com>
Date:   Mon, 29 Aug 2016 17:17:16 +0530
From:   Kishon Vijay Abraham I <kishon@...com>
To:     Arnd Bergmann <arnd@...db.de>,
        <linux-arm-kernel@...ts.infradead.org>
CC:     Gabriele Paoloni <gabriele.paoloni@...wei.com>,
        David Daney <david.daney@...ium.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        Carlos Palminha <CARLOS.PALMINHA@...opsys.com>,
        Thierry Reding <thierry.reding@...il.com>,
        Tanmay Inamdar <tinamdar@....com>,
        Joao Pinto <Joao.Pinto@...opsys.com>,
        Pratyush Anand <pratyush.anand@...il.com>,
        Murali Karicheri <m-karicheri2@...com>,
        Jason Cooper <jason@...edaemon.net>,
        Simon Horman <horms@...ge.net.au>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        Mingkai Hu <mingkai.hu@...escale.com>,
        "linux-omap@...r.kernel.org" <linux-omap@...r.kernel.org>,
        Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
        Jingoo Han <jingoohan1@...il.com>,
        Richard Zhu <Richard.Zhu@...escale.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Stanimir Varbanov <svarbanov@...sol.com>,
        Minghuan Lian <minghuan.Lian@...escale.com>,
        Zhou Wang <wangzhou1@...ilicon.com>,
        Ley Foon Tan <lftan@...era.com>,
        Roy Zang <tie-fei.zang@...escale.com>,
        Lucas Stach <l.stach@...gutronix.de>
Subject: Re: Support for configurable PCIe endpoint

Hi Arnd,

On Thursday 25 August 2016 06:29 PM, Arnd Bergmann wrote:
> On Thursday, August 18, 2016 6:44:09 PM CEST Kishon Vijay Abraham I wrote:
>> Hi Arnd,
>>
>> On Thursday 04 August 2016 04:43 PM, Arnd Bergmann wrote:
>>> On Thursday, August 4, 2016 3:32:01 PM CEST Kishon Vijay Abraham I wrote:
>>>> On Wednesday 03 August 2016 07:09 PM, Joao Pinto wrote:
>>>>>
>>>>> You are rising a topic that we are also addressing in Synopsys.
>>>>>
>>>>> For the PCIe RC hardware validation we are currently using the standard
>>>>> pcie-designware and pcie-designware-plat drivers.
>>>>>
>>>>> For the Endpoint we have to use an internal software package. Its main purpose
>>>>> is to initialize the IP registers, eDMA channels and make data transfer to prove
>>>>> that the everything is working properly. This is done in 2 levels, a custom
>>>>> driver built and loaded and an application that makes some ioctl to the driver
>>>>> executing some interesting functions to check the Endpoint status and make some
>>>>> data exchange.
>>>>
>>>> hmm.. the platform I have doesn't have a DMA in PCIe IP
>>>> (http://www.ti.com/lit/ug/spruhz6g/spruhz6g.pdf). So in your testing does the
>>>> EP access RC memory? i.e the driver in the RC allocates memory from it's DDR
>>>> and gives it's DDR address to the EP. The EP then transfers data to this
>>>> address. (This is a typical use case with ethernet PCIe cards). IIUC that's not
>>>> simple with configurable EPs. I'd like to know more about your testing though.
>>>
>>>
>>> What's the difference between using the EDMA on that chip or a DMA engine
>>> that is part of the PCIe bridge?
>>
>> Do you mean the difference between using DMA on an EP (like ethernet card or
>> sata card) and DMA on PCI RC system? or is it the difference between eDMA
>> within the PCIe IP and system DMA?
> 
> The latter. You write that there is no DMA in the PCIe IP, but from the
> perspective of the RC, it should not matter whether the DMA engine is
> part of the EP logic or behind it.

right, from the RC perspective there is no difference.

What I meant is DMA support in PCIe driver has to be added newly (i.e for
designware) and the the platform I have doesn't have a DMA in PCIe IP. Anyways,
we'll come back to this later after I post my RFC series, maybe by this week end.

Thanks
Kishon