[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAPybu_0bUDRaZKKnEAqEsiBhwuVOqAT_ncWEvJ49BJueKcjH9g@mail.gmail.com>
Date: Thu, 1 Sep 2016 13:29:29 +0200
From: Ricardo Ribalda Delgado <ricardo.ribalda@...il.com>
To: "Ji-Ze Hong (Peter Hong)" <hpeter@...il.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jslaby@...e.com>, Arnd Bergmann <arnd@...db.de>,
Peter Hurley <peter@...leysoftware.com>,
linux-serial@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>,
PA20 TOM TSAI 蔡宗佑
<tom_tsai@...tek.com.tw>, Peter H <peter_hong@...tek.com.tw>,
"Ji-Ze Hong (Peter Hong)" <hpeter+linux_kernel@...il.com>
Subject: Re: [PATCH 7/7] serial: 8250_fintek: Add F81865 Support
Hi Peter
On Thu, Sep 1, 2016 at 5:39 AM, Ji-Ze Hong (Peter Hong)
<hpeter@...il.com> wrote:
>
> switch (pdata->pid) {
> + case CHIP_ID_F81865:
> case CHIP_ID_F81866:
> - sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
> - 0);
> + if (pdata->pid == CHIP_ID_F81866)
> + sio_write_mask_reg(pdata, F81866_FIFO_CTRL,
> + F81866_IRQ_MODE1, 0);
> +
> sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
> F81866_IRQ_SHARE);
> sio_write_mask_reg(pdata, F81866_IRQ_MODE,
What about:
case CHIP_ID_F81866:
sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1, 0);
/* fall through */
case CHIP_ID_F81865:
sio_write_mask_reg(pdata, F81
.....
> @@ -312,6 +318,7 @@ static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
> default: /* No RS485 Auto direction functional */
> break;
>
> + case CHIP_ID_F81865:
> case CHIP_ID_F81866:
> case CHIP_ID_F81216AD:
> case CHIP_ID_F81216H:
> --
> 1.9.1
>
--
Ricardo Ribalda
Powered by blists - more mailing lists