linux-kernel - RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register

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Message-ID: <10c3b7b3a84d8406a7aa44867ea1a124@agner.ch>
Date:   Mon, 05 Sep 2016 12:24:18 -0700
From:   Stefan Agner <stefan@...er.ch>
To:     Meng Yi <meng.yi@....com>
Cc:     dri-devel@...ts.freedesktop.org, alison.wang@...escale.com,
        jianwei.wang.chn@...il.com, linux-kernel@...r.kernel.org,
        stable@...r.kernel.org
Subject: RE: [PATCH] drm/fsl-dcu: fix endian issue when using
 clk_register_divider

On 2016-09-05 01:46, Meng Yi wrote:
>> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
>>
>> Since using clk_register_divider to setup the pixel clock, regmap is no longer
>> used. Regmap did take care of DCU using different endianness. Check
>> endianness using the device-tree property "big-endian" to determine the
>> location of DIV_RATIO.
>>
>> Cc: stable@...r.kernel.org
>> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
>> clock divider")
>> Reported-by: Meng Yi <meng.yi@....com>
>> Signed-off-by: Stefan Agner <stefan@...er.ch>

<snip>

> 
> Tested-by: Meng Yi <meng.yi@....com>
> On LS1021A-TWR board.

Thanks, applied!

--
Stefan