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Message-ID: <3069982.xePB5pcLZB@phil>
Date: Tue, 06 Sep 2016 00:20:58 +0200
From: Heiko Stuebner <heiko@...ech.de>
To: Caesar Wang <wxt@...k-chips.com>
Cc: linux-rockchip@...ts.infradead.org,
Douglas Anderson <dianders@...omium.org>,
sonnyrao@...omium.org, linux-arm-kernel@...ts.infradead.org,
Will Deacon <will.deacon@....com>,
Marc Zyngier <marc.zyngier@....com>,
devicetree@...r.kernel.org, David Wu <david.wu@...k-chips.com>,
Elaine Zhang <zhangqing@...k-chips.com>,
Brian Norris <briannorris@...omium.org>,
linux-kernel@...r.kernel.org, Huang Tao <huangtao@...k-chips.com>,
Shawn Lin <shawn.lin@...k-chips.com>,
Jianqun Xu <jay.xu@...k-chips.com>,
Mark Rutland <mark.rutland@....com>,
Rob Herring <robh+dt@...nel.org>,
Catalin Marinas <catalin.marinas@....com>
Subject: Re: [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
Am Dienstag, 6. September 2016, 02:17:14 CEST schrieb Caesar Wang:
> Add the interrupts cells value for 4, and the 4th cell is zero.
>
> Due to the doc[0] said:" the system requires describing PPI affinity,
> then the value must be at least 4"
> The 4th cell is a phandle to a node describing a set of CPUs this
> interrupt is affine to. The interrupt must be a PPI, and the node
> pointed must be a subnode of the "ppi-partitions" subnode. For
> interrupt types other than PPI or PPIs that are not partitionned,
> this cell must be zero. See the "ppi-partitions" node description
> below.
>
> [0]:
> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
>
> Signed-off-by: Caesar Wang <wxt@...k-chips.com>
> Acked-by: Mark Rutland <mark.rutland@....com>
> Cc: Heiko Stuebner <heiko@...ech.de>
> Cc: Will Deacon <will.deacon@....com>
> Cc: Marc Zyngier <marc.zyngier@....com>
> CC: linux-arm-kernel@...ts.infradead.org
applied to my dts64 branch for 4.9
Thanks
Heiko
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