linux-kernel - RE: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support

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Message-ID: <DB5PR0401MB218327FA907E7224994C09BCE8FA0@DB5PR0401MB2183.eurprd04.prod.outlook.com>
Date:   Fri, 9 Sep 2016 06:48:14 +0000
From:   "S.H. Xie" <shaohui.xie@....com>
To:     Mark Rutland <mark.rutland@....com>
CC:     "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "will.deacon@....com" <will.deacon@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "arnd@...db.de" <arnd@...db.de>, Vincent Hu <mingkai.hu@....com>,
        Horia Geanta Neag <horia.geanta@....com>,
        "Mihai Emilian Bantea" <mihai.bantea@....com>,
        "C.H. Zhao" <chenhui.zhao@....com>,
        "Q.Y. Gong" <qianyu.gong@....com>,
        "M.H. Lian" <minghuan.lian@....com>,
        "Z.Q. Hou" <zhiqiang.hou@....com>
Subject: RE: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support

> > +	pmu {
> > +		compatible = "arm,armv8-pmuv3";
> > +		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> > +			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> > +			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> > +			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> > +		interrupt-affinity = <&cpu0>,
> > +				     <&cpu1>,
> > +				     <&cpu2>,
> > +				     <&cpu3>;
> > +	};
> 
> The compatible string should be "arm,cortex-a72-pmu".
[S.H] Will fix it in next version.

Thanks,
Shaohui