| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Wed, 14 Sep 2016 14:48:56 -0500
From: Han Xu <xhnjupt@...il.com>
To: Yunhui Cui <B56489@...escale.com>
Cc: David Woodhouse <dwmw2@...radead.org>,
Brian Norris <computersforpeace@...il.com>,
"han.xu@...escale.com" <han.xu@...escale.com>,
jagannadh.teki@...il.com, Yunhui Cui <yunhui.cui@....com>,
"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Yao Yuan <yao.yuan@....com>
Subject: Re: [PATCH v3 7/9] mtd: fsl-quadspi: Solve Micron Spansion flash
command conflict
On Thu, Aug 18, 2016 at 2:38 AM, Yunhui Cui <B56489@...escale.com> wrote:
> From: Yunhui Cui <yunhui.cui@....com>
>
> Add some lut_tables to support quad mode for flash n25q128
> on the board ls1021a-twr and solve flash Spansion and Micron
> command conflict.
> In switch {}, The value of command SPINOR_OP_RD_EVCR and
> SPINOR_OP_SPANSION_RDAR is the same. They have to share
> the same seq_id: SEQID_RDAR_OR_RD_EVCR.
>
> Signed-off-by: Yunhui Cui <yunhui.cui@....com>
> ---
> drivers/mtd/spi-nor/fsl-quadspi.c | 47 ++++++++++++++++++++++++++++++---------
> 1 file changed, 36 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 57eed3c..f9a7d4b 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -207,9 +207,9 @@
> #define SEQID_RDCR 9
> #define SEQID_EN4B 10
> #define SEQID_BRWR 11
> -#define SEQID_RDAR 12
> +#define SEQID_RDAR_OR_RD_EVCR 12
> #define SEQID_WRAR 13
> -
> +#define SEQID_WD_EVCR 14
>
> #define QUADSPI_MIN_IOMAP SZ_4M
>
> @@ -393,6 +393,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
> int rxfifo = q->devtype_data->rxfifo;
> u32 lut_base;
> int i;
> + const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
>
> struct spi_nor *nor = &q->nor[0];
> u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
> @@ -489,16 +490,26 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
> qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
> base + QUADSPI_LUT(lut_base));
>
> +
> /*
> - * Read any device register.
> - * Used for Spansion S25FS-S family flash only.
> + * Flash Micron and Spansion command confilict
> + * use the same value 0x65. But it indicates different meaning.
> */
> - lut_base = SEQID_RDAR * 4;
> - qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
> - LUT1(ADDR, PAD1, ADDR24BIT),
> - base + QUADSPI_LUT(lut_base));
> - qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
> - base + QUADSPI_LUT(lut_base + 1));
> + lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
> + if (devtype_data->devtype == FSL_QUADSPI_LS2080A) {
> + /*
> + * Read any device register.
> + * Used for Spansion S25FS-S family flash only.
> + */
> + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
> + LUT1(ADDR, PAD1, ADDR24BIT),
> + base + QUADSPI_LUT(lut_base));
> + qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
> + base + QUADSPI_LUT(lut_base + 1));
> + } else {
> + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
> + base + QUADSPI_LUT(lut_base));
> + }
>
> /*
> * Write any device register.
> @@ -511,6 +522,11 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
> qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
> base + QUADSPI_LUT(lut_base + 1));
>
> + /* Write EVCR register */
> + lut_base = SEQID_WD_EVCR * 4;
> + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
> + base + QUADSPI_LUT(lut_base));
> +
> fsl_qspi_lock_lut(q);
> }
>
> @@ -523,8 +539,15 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
> case SPINOR_OP_READ_FAST:
> case SPINOR_OP_READ4_FAST:
> return SEQID_READ;
> + /*
> + * Spansion & Micron use the same command value 0x65
> + * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
> + * Micron: SPINOR_OP_RD_EVCR,
> + * read enhanced volatile configuration register.
> + * case SPINOR_OP_RD_EVCR:
> + */
> case SPINOR_OP_SPANSION_RDAR:
> - return SEQID_RDAR;
> + return SEQID_RDAR_OR_RD_EVCR;
> case SPINOR_OP_SPANSION_WRAR:
> return SEQID_WRAR;
> case SPINOR_OP_WREN:
> @@ -550,6 +573,8 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
> return SEQID_EN4B;
> case SPINOR_OP_BRWR:
> return SEQID_BRWR;
> + case SPINOR_OP_WD_EVCR:
> + return SEQID_WD_EVCR;
> default:
> if (cmd == q->nor[0].erase_opcode)
> return SEQID_SE;
> --
> 2.1.0.27.g96db324
>
>
Acked-by: Han xu <han.xu@....com>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--
Sincerely,
Han XU
Powered by blists - more mailing lists