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Message-ID: <CACbG30_cKCS7Tz2GSosybPycEgGP444U8ebU8_A_AVr84JDs7g@mail.gmail.com>
Date: Sat, 8 Oct 2016 12:12:07 -0500
From: Nilay Vaish <nilayvaish@...il.com>
To: Fenghua Yu <fenghua.yu@...el.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
"H. Peter Anvin" <h.peter.anvin@...el.com>,
Ingo Molnar <mingo@...e.hu>, Tony Luck <tony.luck@...el.com>,
Peter Zijlstra <peterz@...radead.org>,
Stephane Eranian <eranian@...gle.com>,
Borislav Petkov <bp@...e.de>,
Dave Hansen <dave.hansen@...el.com>, Shaohua Li <shli@...com>,
David Carrillo-Cisneros <davidcc@...gle.com>,
Ravi V Shankar <ravi.v.shankar@...el.com>,
Sai Prakhya <sai.praneeth.prakhya@...el.com>,
Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH v3 05/18] Documentation, x86: Documentation for Intel
resource allocation user interface
On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@...el.com> wrote:
> From: Fenghua Yu <fenghua.yu@...el.com>
>
> +L3 details (code and data prioritization disabled)
> +--------------------------------------------------
> +With CDP disabled the L3 schemata format is:
> +
> + L3:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
> +
> +L3 details (CDP enabled via mount option to resctrl)
> +----------------------------------------------------
> +When CDP is enabled, you need to specify separate cache bit masks for
> +code and data access. The generic format is:
> +
> + L3:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
Can we drop L3 here and instead say:
L<level>:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
and similarly for without CDP as well.
--
Nilay
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