linux-kernel - Re: [PATCH v3 04/18] x86/intel

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Message-ID: <CACbG309kJa-6pAB_7K4GaJEPB7Tw0fQxd=_5+oWtZm1kCaAtHA@mail.gmail.com>
Date:   Sat, 8 Oct 2016 12:11:22 -0500
From:   Nilay Vaish <nilayvaish@...il.com>
To:     Fenghua Yu <fenghua.yu@...el.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        "H. Peter Anvin" <h.peter.anvin@...el.com>,
        Ingo Molnar <mingo@...e.hu>, Tony Luck <tony.luck@...el.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Stephane Eranian <eranian@...gle.com>,
        Borislav Petkov <bp@...e.de>,
        Dave Hansen <dave.hansen@...el.com>, Shaohua Li <shli@...com>,
        David Carrillo-Cisneros <davidcc@...gle.com>,
        Ravi V Shankar <ravi.v.shankar@...el.com>,
        Sai Prakhya <sai.praneeth.prakhya@...el.com>,
        Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
        linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery

On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@...el.com> wrote:
> From: Fenghua Yu <fenghua.yu@...el.com>
>
> Check CPUID leaves for all the Resource Director Technology (RDT)
> Cache Allocation Technology (CAT) bits.
>
> Prescence of allocation features:

Presence

> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 92a8308..64dd8274 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -196,6 +196,10 @@
>
>  #define X86_FEATURE_INTEL_PT   ( 7*32+15) /* Intel Processor Trace */
>
> +#define X86_FEATURE_CAT_L3     ( 7*32+16) /* Cache Allocation Technology L3 */
> +#define X86_FEATURE_CAT_L2     ( 7*32+17) /* Cache Allocation Technology L2 */
> +#define X86_FEATURE_CDP_L3     ( 7*32+18) /* Code and Data Prioritization L3 */
> +
>  /* Virtualization flags: Linux defined, word 8 */
>  #define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */
>  #define X86_FEATURE_VNMI        ( 8*32+ 1) /* Intel Virtual NMI */
> @@ -220,6 +224,7 @@
>  #define X86_FEATURE_RTM                ( 9*32+11) /* Restricted Transactional Memory */
>  #define X86_FEATURE_CQM                ( 9*32+12) /* Cache QoS Monitoring */
>  #define X86_FEATURE_MPX                ( 9*32+14) /* Memory Protection Extension */
> +#define X86_FEATURE_RDT_A      ( 9*32+15) /* Resource Director Technology Allocation */
>  #define X86_FEATURE_AVX512F    ( 9*32+16) /* AVX-512 Foundation */
>  #define X86_FEATURE_AVX512DQ   ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
>  #define X86_FEATURE_RDSEED     ( 9*32+18) /* The RDSEED instruction */

I think these #defines are specific to Intel.  I would prefer if we
have _INTEL_ somewhere in them.

--
Nilay