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Message-ID: <CACbG309=ERARyRQCxWG6GrgRG91TPcSOO-ieTzBEe7d94uM=hg@mail.gmail.com>
Date: Sat, 8 Oct 2016 12:11:08 -0500
From: Nilay Vaish <nilayvaish@...il.com>
To: Fenghua Yu <fenghua.yu@...el.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
"H. Peter Anvin" <h.peter.anvin@...el.com>,
Ingo Molnar <mingo@...e.hu>, Tony Luck <tony.luck@...el.com>,
Peter Zijlstra <peterz@...radead.org>,
Stephane Eranian <eranian@...gle.com>,
Borislav Petkov <bp@...e.de>,
Dave Hansen <dave.hansen@...el.com>, Shaohua Li <shli@...com>,
David Carrillo-Cisneros <davidcc@...gle.com>,
Ravi V Shankar <ravi.v.shankar@...el.com>,
Sai Prakhya <sai.praneeth.prakhya@...el.com>,
Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH v3 01/18] Documentation, ABI: Add a document entry for
cache id
On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@...el.com> wrote:
> From: Fenghua Yu <fenghua.yu@...el.com>
>
> Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id.
>
> Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
> Signed-off-by: Tony Luck <tony.luck@...el.com>
> ---
> Documentation/ABI/testing/sysfs-devices-system-cpu | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
> index 4987417..b1c3d69 100644
> --- a/Documentation/ABI/testing/sysfs-devices-system-cpu
> +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
> @@ -272,6 +272,22 @@ Description: Parameters for the CPU cache attributes
> the modified cache line is written to main
> memory only when it is replaced
>
> +
> +What: /sys/devices/system/cpu/cpu*/cache/index*/id
> +Date: September 2016
> +Contact: Linux kernel mailing list <linux-kernel@...r.kernel.org>
> +Description: Cache id
> +
> + The id provides a unique name for a specific instance of
> + a cache of a particular type. E.g. there may be a level
> + 3 unified cache on each socket in a server and we may
> + assign them ids 0, 1, 2, ...
> +
> + Note that id value may not be contiguous. E.g. level 1
> + caches typically exist per core, but there may not be a
> + power of two cores on a socket, so these caches may be
> + numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...
> +
While it is ok that the caches are not numbered contiguously, it is
unclear how this is related to number of cores on a socket being a
power of 2 or not.
--
Nilay
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