linux-kernel - Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN

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Message-ID: <alpine.DEB.2.20.1610201154020.5073@nanos>
Date:   Thu, 20 Oct 2016 11:57:03 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Bin Gao <bin.gao@...ux.intel.com>
cc:     Ingo Molnar <mingo@...hat.com>, "H. Peter Anvin" <hpa@...or.com>,
        John Stultz <john.stultz@...aro.org>,
        Peter Zijlstra <peterz@...radead.org>, x86@...nel.org,
        linux-kernel@...r.kernel.org, bin.gao@...el.com
Subject: Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag

On Thu, 13 Oct 2016, Bin Gao wrote:
> @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
>  		}
>  	}
>  
> +	setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> +
> +	/*
> +	 * For Atom SoCs TSC is the only reliable clocksource.
> +	 * Mark TSC reliable so no watchdog on it.
> +	 */
> +	if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> +		setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> +

Right. That's what I wanted to see, but please split this into two patches:

  #1 Split the TSC flags
  #2 Set the flag for Goldmont

We do not mix design changes with hw support changes.

Thanks,

	tglx