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Message-ID: <alpine.DEB.2.20.1611031052190.5885@nanos>
Date:   Thu, 3 Nov 2016 11:00:30 -0600 (MDT)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
cc:     mingo@...hat.com, hpa@...or.com, x86@...nel.org, bp@...e.de,
        dave.hansen@...ux.intel.com, lukasz.daniluk@...el.com,
        james.h.cownie@...el.com, jacob.jun.pan@...el.com,
        Piotr.Luc@...el.com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and
 PHIR3MWAIT bit

On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
>  
> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */

Oh well. I asked you to make that whole PHI thing go away.

This is a feature which has nothing to do with PHI. It just happens to be
implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI specific.

It's all about a feature which enables ring 3 mwait/monitor.

> +#define MSR_MISC_FEATURE_ENABLES	0x00000140
> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT	1
> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT	(1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT)
> +

You really try hard to get your crap behind me. Stop sending out half baken
shit every other day without addressing my review comments.

Your trust level approaches negative space.

Thanks,

	tglx

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