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Message-ID: <ED52C51D9B87F54892CE544909A13C6C1FF681C0@IRSMSX101.ger.corp.intel.com>
Date: Fri, 4 Nov 2016 06:47:02 +0000
From: "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@...el.com>
To: Thomas Gleixner <tglx@...utronix.de>
CC: "mingo@...hat.com" <mingo@...hat.com>,
"hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
"bp@...e.de" <bp@...e.de>,
"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
"Daniluk, Lukasz" <lukasz.daniluk@...el.com>,
"Cownie, James H" <james.h.cownie@...el.com>,
"Pan, Jacob jun" <jacob.jun.pan@...el.com>,
"Luc, Piotr" <Piotr.Luc@...el.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and
PHIR3MWAIT bit
>>On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
>>
>> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
>
>Oh well. I asked you to make that whole PHI thing go away.
>
>This is a feature which has nothing to do with PHI. It just happens to be implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI specific.
>
>It's all about a feature which enables ring 3 mwait/monitor.
This bit enables ring 3 MONITOR/MWAIT only on Xeon Phi. It is reserved for other architectures.
I think this will be confusing when I remove PHI.
>> +#define MSR_MISC_FEATURE_ENABLES 0x00000140
>> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT 1
>> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT)
>> +
>
>You really try hard to get your crap behind me. Stop sending out half baken shit every other day without addressing my review comments.
>
>Your trust level approaches negative space.
>
>Thanks,
>
> tglx
Regards,
Grzegorz
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