linux-kernel - RE: [PATCH 3/3] clk: qcom: Set BRANCH_HALT

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Message-ID: <001701d23b02$7bf7daa0$73e78fe0$@codeaurora.org>
Date:   Thu, 10 Nov 2016 08:58:13 +0530
From:   "Sricharan" <sricharan@...eaurora.org>
To:     "'Rajendra Nayak'" <rnayak@...eaurora.org>,
        "'Stephen Boyd'" <sboyd@...eaurora.org>
Cc:     <mturquette@...libre.com>, <linux-clk@...r.kernel.org>,
        <linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <stanimir.varbanov@...aro.org>
Subject: RE: [PATCH 3/3] clk: qcom: Set BRANCH_HALT_DELAY flags for venus core0/1 clks

Hi Rajendra,
>
>>>
>>> The proper sequence sounds like it should be:
>>>
>>> 	1. Enable GDSC for main domain
>>> 	2. Enable clocks for main domain (video_{core,maxi,ahb,axi}_clk)
>>> 	3. Write the two registers to assert hw signal for subdomains
>>> 	4. Enable GDSCs for two subdomains
>>> 	5. Enable clocks for subdomains (video_subcore{0,1}_clk)
>>>
>[]..
>
>>
>> So the above is the sequence which is actually carried out on the
>> firmware side. The same can be done in host as well.
>
>By the 'above sequence is done on firmware side', I hope you don;t mean *all* 5 steps.
>I guess you mean only step 3 is done by firmware?
>

Yes, only step 3.

Regards,
 Sricharan