linux-kernel - Re: [PATCH 3/3] clk: qcom: Set BRANCH_HALT

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Message-ID: <5823DC3E.2060106@codeaurora.org>
Date:   Thu, 10 Nov 2016 08:02:30 +0530
From:   Rajendra Nayak <rnayak@...eaurora.org>
To:     Sricharan <sricharan@...eaurora.org>,
        'Stephen Boyd' <sboyd@...eaurora.org>
CC:     mturquette@...libre.com, linux-clk@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        stanimir.varbanov@...aro.org
Subject: Re: [PATCH 3/3] clk: qcom: Set BRANCH_HALT_DELAY flags for venus
 core0/1 clks


[]..

>>
>> The proper sequence sounds like it should be:
>>
>> 	1. Enable GDSC for main domain
>> 	2. Enable clocks for main domain (video_{core,maxi,ahb,axi}_clk)
>> 	3. Write the two registers to assert hw signal for subdomains
>> 	4. Enable GDSCs for two subdomains
>> 	5. Enable clocks for subdomains (video_subcore{0,1}_clk)
>>
[]..

> 
> So the above is the sequence which is actually carried out on the
> firmware side. The same can be done in host as well.

By the 'above sequence is done on firmware side', I hope you don;t mean *all* 5 steps.
I guess you mean only step 3 is done by firmware?

> The clocks stuck issue indeed is not there with this. But with the
> above sequence we need to add a step to do inverse of STEP3
> above (ie write the registers to de-assert hw_signal), to keep
> the subdomains in off, till firmware uses it. So the above sequence
> helps to avoid masking the halt check, although the host really
> does not wants to use these clocks, except setting it up for the
> firmware.

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