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Message-ID: <5c1909c9-6132-68b8-8e7e-c2d32f215c09@amd.com>
Date: Thu, 17 Nov 2016 09:50:25 -0600
From: "Natarajan, Janakarajan" <Janakarajan.Natarajan@....com>
To: Ingo Molnar <mingo@...nel.org>
CC: <linux-kernel@...r.kernel.org>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
"Suravee Suthikulpanit" <suravee.suthikulpanit@....com>
Subject: Re: [PATCH] Support for perf on AMD family17h processors
On 11/17/2016 12:46 AM, Ingo Molnar wrote:
> * Janakarajan Natarajan <Janakarajan.Natarajan@....com> wrote:
>
>> This patch enables perf core PMU support for AMD family17h processors. In
>> family17h, there is no PMC-event constraint. All events, irrespective of the
>> type, can be measured using any of the performance counters.
> BTW., that's a very nice hardware design that simplifies counter constraints and
> scheduling!
>
> Does Fam17h have 6 generic counters per core, like Fam15h?
Yes. Fam17h has 6 generic core counters.
>
> Thanks,
>
> Ingo
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