linux-kernel - Re: Tearing down DMA transfer setup after DMA client has finished

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Message-ID: <cba10848-57b1-c28c-2a60-83eb9da4cc63@free.fr>
Date:   Fri, 25 Nov 2016 16:21:49 +0100
From:   Mason <slash.tmp@...e.fr>
To:     Mans Rullgard <mans@...sr.com>
Cc:     Russell King - ARM Linux <linux@...linux.org.uk>,
        Vinod Koul <vinod.koul@...el.com>,
        Lars-Peter Clausen <lars@...afoo.de>,
        Dave Jiang <dave.jiang@...el.com>,
        Arnd Bergmann <arnd@...db.de>, Mark Brown <broonie@...nel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
        LKML <linux-kernel@...r.kernel.org>,
        Laurent Pinchart <laurent.pinchart@...asonboard.com>,
        dmaengine@...r.kernel.org, Dan Williams <dan.j.williams@...el.com>,
        Jon Mason <jdmason@...zu.us>, Lee Jones <lee.jones@...aro.org>,
        Maxime Ripard <maxime.ripard@...e-electrons.com>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>
Subject: Re: Tearing down DMA transfer setup after DMA client has finished

On 25/11/2016 16:12, Måns Rullgård wrote:

> Mason writes:
> 
>> I've had several talks with the HW dev, and I don't think they
>> anticipated the need to mux the 3 channels. In their minds,
>> customers would choose at most 3 devices to support, and
>> assign one channel to each device statically.
>>
>> In fact, in tango4, supported devices are:
>> A) NAND Flash controllers 0 and 1
>> NB: the upstream driver only uses controller 0
>> B) IDE or SATA controllers 0 and 1
>> C) a few crypto HW blocks which do not work as expected (unused)
>>
>> Customers typically use 1 channel for NAND, maybe 1 for SATA,
>> and 1 channel remains unused.
> 
> The hardware has two sata controllers, and I have a board that uses both.

I don't have the tango3 client devices in mind, but
1 NAND + 2 SATA works out alright for 3 channels, right?

Regards.