linux-kernel - Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont

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Date:   Tue, 6 Dec 2016 13:38:48 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     Andi Kleen <andi@...stfloor.org>
Cc:     linux-kernel@...r.kernel.org, Andi Kleen <ak@...ux.intel.com>,
        alexander.shishkin@...el.com, kan.liang@...el.com,
        stable@...r.kernel.org
Subject: Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont


For some reason this patch never hit my inbox, it could be because
you're wrecked the Cc line and either infradead or my mta dropped the
email because of that.

On Fri, Dec 02, 2016 at 03:17:32PM -0800, Andi Kleen wrote:
> From: Andi Kleen <ak@...ux.intel.com>
> 
> The earlier patch ccbebba4 allowed enabling PT and LBR at the same

SHAs should be 12 chars.

> time on Goldmont. However it also allowed enabling BTS and LBR
> at the same time, which is still not supported. Fix this by
> bypassing the check only for PT.
> 
> Marking for stable because this allows crashing kernels. Also
> should be merged for 4.9.
> 
> Fixes: ccbebba4 ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")

same

> Cc: alexander.shishkin@...el.com
> Cc: kan.liang@...el.com
> Cc: stable@...r.kernel.org # 4.6+
> Signed-off-by: Andi Kleen <ak@...ux.intel.com>
> ---
>  arch/x86/events/core.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> index d0efb5cb1b00..baa1eed55e88 100644
> --- a/arch/x86/events/core.c
> +++ b/arch/x86/events/core.c
> @@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
>  {
>  	int i;
>  
> -	if (x86_pmu.lbr_pt_coexist)
> +	if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
>  		return 0;

This would also allow PT & BTS at the same time, is that a supported
configuration?

>  
>  	if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {