linux-kernel - Re: [patch 2/3] x86/process: Optimize TIF

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CALCETrUaVrHYS5Jf3+ez4LN_X=_LFmVxhFwkn9JnKcJXGX6uZQ@mail.gmail.com>
Date:   Thu, 15 Dec 2016 09:28:52 -0800
From:   Andy Lutomirski <luto@...capital.net>
To:     Thomas Gleixner <tglx@...utronix.de>
Cc:     LKML <linux-kernel@...r.kernel.org>, X86 ML <x86@...nel.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Kyle Huey <khuey@...ehuey.com>,
        Andy Lutomirski <luto@...nel.org>
Subject: Re: [patch 2/3] x86/process: Optimize TIF_BLOCKSTEP switch

On Thu, Dec 15, 2016 at 8:44 AM, Thomas Gleixner <tglx@...utronix.de> wrote:
> Provide and use a seperate helper for toggling the DEBUGCTLMSR_BTF bit
> instead of doing it open coded with a branch and eventually evaluating
> boot_cpu_data twice.
>
> x86_64:
> 3694       8505      16   12215    2fb7 Before
> 3662       8505      16   12183    2f97 After
>
> i386:
> 5986       9388    1804   17178    431a Before
> 5906       9388    1804   17098    42ca After
>
> Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
> ---
>  arch/x86/include/asm/processor.h |   12 ++++++++++++
>  arch/x86/kernel/process.c        |   10 ++--------
>  2 files changed, 14 insertions(+), 8 deletions(-)
>
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -676,6 +676,18 @@ static inline void update_debugctlmsr(un
>         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
>  }
>
> +static inline void toggle_debugctlmsr(unsigned long mask)
> +{
> +       unsigned long msrval;
> +
> +#ifndef CONFIG_X86_DEBUGCTLMSR
> +       if (boot_cpu_data.x86 < 6)
> +               return;
> +#endif
> +       rdmsrl(MSR_IA32_DEBUGCTLMSR, msrval);
> +       wrmsrl(MSR_IA32_DEBUGCTLMSR, msrval ^ mask);
> +}
> +

This scares me.  If the MSR ever gets out of sync with the TI flag,
this will malfunction.  And IIRC the MSR is highly magical and the CPU
clears it all by itself under a variety of not-so-well documented
circumstances.

How about adding a real feature bit and doing:

if (!static_cpu_has(X86_FEATURE_BLOCKSTEP))
  return;

rdmsrl(MSR_IA32_DEBUGCTLMSR, msrval);
msrval &= DEBUGCTLMSR_BTF;
msrval |= (tifn >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BIT;

--Andy