linux-kernel - Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers

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Message-ID: <CACRpkdY-Hn7eZVKORgDF7kSFSc7PrAPdENscjkj94WtWJPXBww@mail.gmail.com>
Date:   Tue, 27 Dec 2016 23:16:48 +0100
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Andrew Jeffery <andrew@...id.au>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Lee Jones <lee.jones@...aro.org>,
        Joel Stanley <joel@....id.au>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and
 GFX controllers

On Tue, Dec 20, 2016 at 8:35 AM, Andrew Jeffery <andrew@...id.au> wrote:

> The System Control Unit IP block in the Aspeed SoCs is typically where
> the pinmux configuration is found, but not always. A number of pins
> depend on state in one of LPC Host Control (LHC) or SoC Display
> Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
> means to adjust these as necessary.
>
> We use syscon to cast a regmap over the GFX and LPC blocks, which is
> used as an arbitration layer between the relevant driver and the pinctrl
> subsystem. The regmaps are then exposed to the SoC-specific pinctrl
> drivers by phandles in the devicetree, and are selected during a mux
> request by querying a new 'ip' member in struct aspeed_sig_desc.
>
> Signed-off-by: Andrew Jeffery <andrew@...id.au>
> Reviewed-by: Joel Stanley <joel@....id.au>

Patch applied, adding Rob's ack in the process.

Yours,
Linus Walleij