linux-kernel - Re: [PATCH 3/2] x86/microcode/intel: Add a helper which gives the microcode revision

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CALCETrVnUbiZZabLZkhQHadzJ_cdbdVoUW3RTcNnZz8CGnsjNg@mail.gmail.com>
Date:   Wed, 28 Dec 2016 10:12:22 -0800
From:   Andy Lutomirski <luto@...capital.net>
To:     Borislav Petkov <bp@...en8.de>
Cc:     Junichi Nomura <j-nomura@...jp.nec.com>,
        Boris Ostrovsky <boris.ostrovsky@...cle.com>,
        "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>
Subject: Re: [PATCH 3/2] x86/microcode/intel: Add a helper which gives the
 microcode revision

On Wed, Dec 28, 2016 at 4:53 AM, Borislav Petkov <bp@...en8.de> wrote:
> On Wed, Dec 28, 2016 at 12:21:20PM +0100, Borislav Petkov wrote:
>> From: Borislav Petkov <bp@...e.de>
>>
>> Intel supplies the microcode revision value in MSR 0x8b
>> (IA32_BIOS_SIGN_ID) after CPUID(1) has been executed. Execute it each
>> time before reading that MSR.
>
> And then, we can go a step further and even do a separate helper which does the
> required steps to read out the microcode revision so that we don't forget them
> next time we change the code.
>
> Provided that works for xen, though, because I need to do the native
> variants but early_init_intel() can call the paravirt *msr() versions
> and I have no idea whether that's kosher on xen pv.
>
> Boris, any objections?
>
> ---
> From: Borislav Petkov <bp@...e.de>
> Date: Wed, 28 Dec 2016 13:44:56 +0100
> Subject: [PATCH] x86/microcode/intel: Add a helper which gives the microcode
>  revision
>
> Since on Intel we're required to do CPUID(1) first, before reading
> the microcode revision MSR, let's add a special helper which does the
> required steps so that we don't forget to do them next time, when we
> want to read the microcode revision.
>
> Signed-off-by: Borislav Petkov <bp@...e.de>
> ---
>  arch/x86/include/asm/microcode_intel.h | 15 ++++++++++++
>  arch/x86/kernel/cpu/intel.c            | 11 +++------
>  arch/x86/kernel/cpu/microcode/intel.c  | 43 ++++++++++------------------------
>  3 files changed, 31 insertions(+), 38 deletions(-)
>
> diff --git a/arch/x86/include/asm/microcode_intel.h b/arch/x86/include/asm/microcode_intel.h
> index 195becc6f780..e793fc9a9b20 100644
> --- a/arch/x86/include/asm/microcode_intel.h
> +++ b/arch/x86/include/asm/microcode_intel.h
> @@ -52,6 +52,21 @@ struct extended_sigtable {
>
>  #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
>
> +static inline u32 intel_get_microcode_revision(void)
> +{
> +       u32 rev, dummy;
> +
> +       native_wrmsrl(MSR_IA32_UCODE_REV, 0);
> +
> +       /* As documented in the SDM: Do a CPUID 1 here */
> +       native_cpuid_eax(1);

As in the other email, could this just be native_cpuid()?

--Andy