linux-kernel - Re: [PATCH RFC 0/4] 5-level EPT

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Message-ID: <181888.1483043916@turing-police.cc.vt.edu>
Date:   Thu, 29 Dec 2016 15:38:36 -0500
From:   Valdis.Kletnieks@...edu
To:     Liang Li <liang.z.li@...el.com>
Cc:     kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
        tglx@...utronix.de, mingo@...hat.com,
        kirill.shutemov@...ux.intel.com, dave.hansen@...ux.intel.com,
        guangrong.xiao@...ux.intel.com, pbonzini@...hat.com,
        rkrcmar@...hat.com
Subject: Re: [PATCH RFC 0/4] 5-level EPT

On Thu, 29 Dec 2016 17:25:59 +0800, Liang Li said:
> x86-64 is currently limited physical address width to 46 bits, which
> can support 64 TiB of memory. Some vendors require to support more for
> some use case. Intel plans to extend the physical address width to
> 52 bits in some of the future products.

Can you explain why this patchset mentions 52 bits in some places,
and 57 in others?  Is it because there are currently in-process
chipsets that will do 52, but you want to future-proof it by extending
it to 57 so future chipsets won't need more work?  Or is there some other
reason?

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