linux-kernel - RE: [PATCH RFC 0/4] 5-level EPT

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Message-ID: <F2CBF3009FA73547804AE4C663CAB28E3C349D5E@shsmsx102.ccr.corp.intel.com>
Date:   Fri, 30 Dec 2016 01:26:57 +0000
From:   "Li, Liang Z" <liang.z.li@...el.com>
To:     "Valdis.Kletnieks@...edu" <Valdis.Kletnieks@...edu>
CC:     "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "guangrong.xiao@...ux.intel.com" <guangrong.xiao@...ux.intel.com>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "rkrcmar@...hat.com" <rkrcmar@...hat.com>
Subject: RE: [PATCH RFC 0/4] 5-level EPT

> Subject: Re: [PATCH RFC 0/4] 5-level EPT
> 
> On Thu, 29 Dec 2016 17:25:59 +0800, Liang Li said:
> > x86-64 is currently limited physical address width to 46 bits, which
> > can support 64 TiB of memory. Some vendors require to support more for
> > some use case. Intel plans to extend the physical address width to
> > 52 bits in some of the future products.
> 
> Can you explain why this patchset mentions 52 bits in some places, and 57 in
> others?  Is it because there are currently in-process chipsets that will do 52,
> but you want to future-proof it by extending it to 57 so future chipsets won't
> need more work?  Or is there some other reason?

The 57-bits I referred in  this patch set means the virtual address width which will
be supported in the future CPU with 52-bits physical address width.
5 level EPT can support maximum 57-bits physical address width, as long as the
future CPU use no more than 57-bits physical address width, no more work is needed.

Thanks!
Liang