linux-kernel - Re: [PATCH] usb: dwc2: gadget: Fix GUSBCFG.USBTRDTIM value

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-ID: <26c07f46-795b-d561-72ed-0548b63a98d9@st.com>
Date:   Thu, 12 Jan 2017 16:41:24 +0100
From:   Amelie DELAUNAY <amelie.delaunay@...com>
To:     John Youn <johnyoun@...opsys.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>
CC:     <linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] usb: dwc2: gadget: Fix GUSBCFG.USBTRDTIM value

Hi all,
Sorry, I did not see Pengcheng Li patch which is exactly the same:
https://patchwork.kernel.org/patch/9347979/

Regards

On 01/12/2017 04:36 PM, Amelie Delaunay wrote:
> USBTrdTim must be programmed to 0x5 when phy has a UTMI+ 16-bit wide
> interface or 0x9 when it has a 8-bit wide interface.
> GUSBCFG reset value (Value After Reset: 0x1400) sets USBTrdTim to 0x5.
> In case of 8-bit UTMI+, without clearing GUSBCFG.USBTRDTIM mask, USBTrdTim
> results in 0xD (0x5 | 0x9).
> That's why we need to clear GUSBCFG.USBTRDTIM mask before setting USBTrdTim
> value, to ensure USBTrdTim is correctly set in case of 8-bit UTMI+.
>
> Signed-off-by: Amelie Delaunay <amelie.delaunay@...com>
> ---
>  drivers/usb/dwc2/gadget.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index c55db4a..86b2076 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -3169,7 +3169,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
>  	/* keep other bits untouched (so e.g. forced modes are not lost) */
>  	usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
>  	usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
> -		GUSBCFG_HNPCAP);
> +		GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
>
>  	if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
>  	    (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
> @@ -4131,7 +4131,7 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
>  	/* keep other bits untouched (so e.g. forced modes are not lost) */
>  	usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
>  	usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
> -		GUSBCFG_HNPCAP);
> +		GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
>
>  	/* set the PLL on, remove the HNP/SRP and set the PHY */
>  	trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
>