linux-kernel - Re: [PATCH] usb: dwc2: gadget: Fix GUSBCFG.USBTRDTIM value

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Message-ID: <cdfd09b6-fa9c-dc2d-2314-4678509cd358@synopsys.com>
Date:   Thu, 12 Jan 2017 15:45:16 -0800
From:   John Youn <John.Youn@...opsys.com>
To:     Amelie DELAUNAY <amelie.delaunay@...com>,
        John Youn <John.Youn@...opsys.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Felipe Balbi <balbi@...nel.org>
CC:     "linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] usb: dwc2: gadget: Fix GUSBCFG.USBTRDTIM value

On 1/12/2017 7:41 AM, Amelie DELAUNAY wrote:
> Hi all,
> Sorry, I did not see Pengcheng Li patch which is exactly the same:
> https://urldefense.proofpoint.com/v2/url?u=https-3A__patchwork.kernel.org_patch_9347979_&d=DgIC-g&c=DPL6_X_6JkXFx7AXWqB0tg&r=U3o8uKoKhWme5_V9D-eeCkB11BFwt4KvWztBgdE9ZpA&m=6VylcKBQDS2RlneASNqb6vUEW48snVAZ1f_mhtzcSaE&s=iYEesI5W2GVN4jBs6pzyRC7Sb0RAng4gpapDsoZQG_s&e= 
> 
> Regards
> 

Hi Felipe,

Could you take either one?

Regards,
John


> On 01/12/2017 04:36 PM, Amelie Delaunay wrote:
>> USBTrdTim must be programmed to 0x5 when phy has a UTMI+ 16-bit wide
>> interface or 0x9 when it has a 8-bit wide interface.
>> GUSBCFG reset value (Value After Reset: 0x1400) sets USBTrdTim to 0x5.
>> In case of 8-bit UTMI+, without clearing GUSBCFG.USBTRDTIM mask, USBTrdTim
>> results in 0xD (0x5 | 0x9).
>> That's why we need to clear GUSBCFG.USBTRDTIM mask before setting USBTrdTim
>> value, to ensure USBTrdTim is correctly set in case of 8-bit UTMI+.
>>
>> Signed-off-by: Amelie Delaunay <amelie.delaunay@...com>
>> ---
>>  drivers/usb/dwc2/gadget.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
>> index c55db4a..86b2076 100644
>> --- a/drivers/usb/dwc2/gadget.c
>> +++ b/drivers/usb/dwc2/gadget.c
>> @@ -3169,7 +3169,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
>>  	/* keep other bits untouched (so e.g. forced modes are not lost) */
>>  	usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
>>  	usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
>> -		GUSBCFG_HNPCAP);
>> +		GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
>>
>>  	if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
>>  	    (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
>> @@ -4131,7 +4131,7 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
>>  	/* keep other bits untouched (so e.g. forced modes are not lost) */
>>  	usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
>>  	usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
>> -		GUSBCFG_HNPCAP);
>> +		GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
>>
>>  	/* set the PLL on, remove the HNP/SRP and set the PHY */
>>  	trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
>>
>