lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <AM4PR0401MB2324085C8FC8BCE5B999C949907D0@AM4PR0401MB2324.eurprd04.prod.outlook.com>
Date:   Mon, 16 Jan 2017 03:12:16 +0000
From:   Bough Chen <haibo.chen@....com>
To:     Ulf Hansson <ulf.hansson@...aro.org>
CC:     Shawn Lin <shawn.lin@...k-chips.com>,
        Clemens Gruber <clemens.gruber@...ruber.com>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        "Adrian Hunter" <adrian.hunter@...el.com>,
        "A.S. Dong" <aisheng.dong@....com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Gary Bisson <gary.bisson@...ndarydevices.com>,
        Fabio Estevam <festevam@...il.com>,
        "Shawn Guo" <shawnguo@...nel.org>
Subject: RE: eMMC boot problem: switch to bus width 8 ddr failed

> -----Original Message-----
> From: Ulf Hansson [mailto:ulf.hansson@...aro.org]
> Sent: Friday, January 13, 2017 7:23 PM
> To: Bough Chen <haibo.chen@....com>
> Cc: Shawn Lin <shawn.lin@...k-chips.com>; Clemens Gruber
> <clemens.gruber@...ruber.com>; linux-mmc@...r.kernel.org; Linus Walleij
> <linus.walleij@...aro.org>; Adrian Hunter <adrian.hunter@...el.com>; A.S.
> Dong <aisheng.dong@....com>; linux-kernel@...r.kernel.org; Gary Bisson
> <gary.bisson@...ndarydevices.com>; Fabio Estevam <festevam@...il.com>;
> Shawn Guo <shawnguo@...nel.org>
> Subject: Re: eMMC boot problem: switch to bus width 8 ddr failed
> 
> [...]
> 
> > Hi Ulf and Shawn,
> >
> > Aisheng and I debug this issue these days, and we find the root cause.
> > There are two things to describe.
> >
> > 1) voltage switch issue.  The properity "no-1-8-v" do not work for
> MMC_TIMING_MMC_DDR52.
> > This is another bug, we need to fix, but has no relation with the current bug.
> 
> I am working on a patch which invents MMC_CAP_3_3V_DDR and which has a
> corresponding DT binding "mmc-ddr-3_3v".
> Give me a day or so, then I will post it.
> 
> Likely it should help to resolve your issue, don't you think?

Seems Yes, I will test the patch when you post.

Best Regards,
Haibo Chen

> 
> [...]
> 
> Kind regards
> Uffe

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ