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Message-ID: <1a244e36-a965-3efb-4413-b40e8c549cf9@osg.samsung.com>
Date: Fri, 20 Jan 2017 07:11:04 -0300
From: Javier Martinez Canillas <javier@....samsung.com>
To: linux-kernel@...r.kernel.org
Cc: Inki Dae <inki.dae@...sung.com>,
Andi Shyti <andi.shyti@...sung.com>,
Shuah Khan <shuahkh@....samsung.com>,
Marek Szyprowski <m.szyprowski@...sung.com>,
Andrzej Hajda <a.hajda@...sung.com>,
devicetree@...r.kernel.org, Kukjin Kim <kgene@...nel.org>,
Russell King <linux@...linux.org.uk>,
linux-samsung-soc@...r.kernel.org,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Krzysztof Kozlowski <krzk@...nel.org>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/2] ARM: dts: exynos: Add CLK_ACLK432_SCALER clock to
gsc_pd for Exynos5800
Hello,
On 01/19/2017 07:29 PM, Javier Martinez Canillas wrote:
> On Exynos5800 SoC the SCALER block uses 2 input clocks: CLK_ACLK_300_GSCL
> and CLK_ACLK432_SCALER, so both needs to be ungated in order to access it.
>
> The SoC manual say the CLK_ACLK432_SCALER is needed to access the internal
> buses, so add this clock as another asynchronous bridges (ASB) clock.
>
> The Exynos5420 only has the CLK_ACLK_300_GSCL clock defined. So just using
> this definition from exynos5420.dtsi in Exynos5800 leads to the following:
>
Please ignore this patch as suggested by Marek. Instead I'll post a patch
to mark the clock as CLK_IS_CRITICAL, as a temporary workaround until a
proper runtime PM based solution gets merged.
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
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