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Message-ID: <tip-0c12d18ab96e4da9f3e963bc242689bdeaaf2330@git.kernel.org>
Date: Mon, 23 Jan 2017 01:08:18 -0800
From: tip-bot for Borislav Petkov <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: tglx@...utronix.de, bp@...e.de, hpa@...or.com, mingo@...nel.org,
linux-kernel@...r.kernel.org
Subject: [tip:x86/mce] x86/microcode: Convert to bare minimum MSR accessors
Commit-ID: 0c12d18ab96e4da9f3e963bc242689bdeaaf2330
Gitweb: http://git.kernel.org/tip/0c12d18ab96e4da9f3e963bc242689bdeaaf2330
Author: Borislav Petkov <bp@...e.de>
AuthorDate: Fri, 20 Jan 2017 21:29:42 +0100
Committer: Thomas Gleixner <tglx@...utronix.de>
CommitDate: Mon, 23 Jan 2017 10:02:45 +0100
x86/microcode: Convert to bare minimum MSR accessors
Having tracepoints to the MSR accessors makes them unsuitable for early
microcode loading: think 32-bit before paging is enabled and us chasing
pointers to test whether a tracepoint is enabled or not. Results in a
reliable triple fault.
Convert to the bare ones.
Signed-off-by: Borislav Petkov <bp@...e.de>
Link: http://lkml.kernel.org/r/20170120202955.4091-4-bp@alien8.de
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
arch/x86/include/asm/microcode.h | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 38711df..90b22bb 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -7,18 +7,17 @@
#define native_rdmsr(msr, val1, val2) \
do { \
- u64 __val = native_read_msr((msr)); \
+ u64 __val = __rdmsr((msr)); \
(void)((val1) = (u32)__val); \
(void)((val2) = (u32)(__val >> 32)); \
} while (0)
#define native_wrmsr(msr, low, high) \
- native_write_msr(msr, low, high)
+ __wrmsr(msr, low, high)
#define native_wrmsrl(msr, val) \
- native_write_msr((msr), \
- (u32)((u64)(val)), \
- (u32)((u64)(val) >> 32))
+ __wrmsr((msr), (u32)((u64)(val)), \
+ (u32)((u64)(val) >> 32))
struct ucode_patch {
struct list_head plist;
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