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Date:   Thu, 26 Jan 2017 16:00:20 -0800
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Rajendra Nayak <rnayak@...eaurora.org>
Cc:     mturquette@...libre.com, linux-clk@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        stanimir.varbanov@...aro.org, sricharan@...eaurora.org
Subject: Re: [PATCH v2] clk: qcom: gdsc: Fix handling of hw control
 enable/disable

On 01/23, Rajendra Nayak wrote:
> Once a gdsc is brought in and out of HW control, there is a
> power down and up cycle which can take upto 1us. Polling on
> the gdsc status immediately after the hw control enable/disable
> can mislead software/firmware to belive the gdsc is already either on
> or off, while its yet to complete the power cycle.
> To avoid this add a 1us delay post a enable/disable of HW control
> mode.
> 
> Also after the HW control mode is disabled, poll on the status to
> check gdsc status reflects its 'on' before force disabling it
> in software.
> 
> Reported-by: Stanimir Varbanov <stanimir.varbanov@...aro.org>
> Signed-off-by: Rajendra Nayak <rnayak@...eaurora.org>
> ---

Applied to clk-next + I added a fixes tag. I don't think any
driver is affected by this problem in mainline, hence the punt to
v4.11.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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