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Message-ID: <8520D5D51A55D047800579B094147198263DC9BE@XAP-PVEXMBX02.xlnx.xilinx.com>
Date: Mon, 30 Jan 2017 05:57:23 +0000
From: Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
To: Marc Zyngier <marc.zyngier@....com>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"paul.gortmaker@...driver.com" <paul.gortmaker@...driver.com>,
"robh@...nel.org" <robh@...nel.org>,
"colin.king@...onical.com" <colin.king@...onical.com>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>
CC: "michal.simek@...inx.com" <michal.simek@...inx.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Ravikiran Gummaluri <rgummal@...inx.com>,
"arnd@...db.de" <arnd@...db.de>
Subject: RE: [PATCH v2 2/2] PCI: Xilinx NWL: Fix, proc interrupts for legacy
virtual irq shown as edge
>
> On 25/01/17 08:52, Bharat Kumar Gogada wrote:
> > - Legacy interrupts are level triggered, virtual irq line of End Point
> > shows as edge in /proc/interrupts.
> > - Setting irq flags of virtual irq line of EP to level triggered at
> > the time of mapping.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@...inx.com>
> > ---
> > drivers/pci/host/pcie-xilinx-nwl.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/pci/host/pcie-xilinx-nwl.c
> > b/drivers/pci/host/pcie-xilinx-nwl.c
> > index 6ac3e1d..1cddd1f 100644
> > --- a/drivers/pci/host/pcie-xilinx-nwl.c
> > +++ b/drivers/pci/host/pcie-xilinx-nwl.c
> > @@ -434,6 +434,7 @@ static int nwl_legacy_map(struct irq_domain
> > *domain, unsigned int irq, {
> > irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
> > irq_set_chip_data(irq, domain->host_data);
> > + irq_set_status_flags(irq, IRQ_LEVEL);
> >
> > return 0;
> > }
> >
>
> As said in my previous review [1], this should be folded in the previous patch, as
> it doesn't make much sense on its own.
>
Agreed, will send in same previous patch.
bharat
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