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Message-ID: <CACRpkdbQu9KkR5_dfKk=1-LWLdQ3dyZdtW1JD3SeZZD1s=X3fg@mail.gmail.com>
Date:   Tue, 31 Jan 2017 15:50:03 +0100
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Andrew Jeffery <andrew@...id.au>
Cc:     Joel Stanley <joel@....id.au>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        OpenBMC Maillist <openbmc@...ts.ozlabs.org>
Subject: Re: [PATCH v3] gpio: aspeed: Add banks Y, Z, AA, AB and AC

On Fri, Jan 27, 2017 at 5:24 AM, Andrew Jeffery <andrew@...id.au> wrote:

> This is less straight-forward than one would hope, as some banks only
> have 4 pins rather than 8, others are output only, yet more (W and
> X, already supported) are input-only, and in the case of the g4 SoC bank
> AC doesn't exist.
>
> Add some structs to describe the varying properties of different banks
> and integrate mechanisms to deny requests for unsupported
> configurations.
>
> Signed-off-by: Andrew Jeffery <andrew@...id.au>
> ---
>
> Since v2:

Patch applied with some patch -p1 < fuzz
please check the result.

Yours,
Linus Walleij

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