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Message-ID: <201702020329.2tbDM1Fc%fengguang.wu@intel.com>
Date:   Thu, 2 Feb 2017 03:37:20 +0800
From:   kbuild test robot <lkp@...el.com>
To:     Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>
Cc:     kbuild-all@...org, tpmdd-devel@...ts.sourceforge.net,
        linux-security-module@...r.kernel.org,
        Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>,
        Peter Huewe <peterhuewe@....de>,
        Marcel Selhorst <tpmdd@...horst.net>,
        Jason Gunthorpe <jgunthorpe@...idianresearch.com>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] tpm: fix parameter order in tpm_getcap()

Hi Jarkko,

[auto build test WARNING on next-20170201]
[cannot apply to char-misc/char-misc-testing v4.9-rc8 v4.9-rc7 v4.9-rc6 v4.10-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Jarkko-Sakkinen/tpm-fix-parameter-order-in-tpm_getcap/20170202-025932
config: x86_64-allyesdebian (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   drivers/char/tpm/tpm_tis_core.c: In function 'tpm_tis_gen_interrupt':
>> drivers/char/tpm/tpm_tis_core.c:561:59: warning: passing argument 4 of 'tpm_getcap' makes integer from pointer without a cast [-Wint-conversion]
      return tpm_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap, desc,
                                                              ^~~~
   In file included from drivers/char/tpm/tpm_tis_core.c:31:0:
   drivers/char/tpm/tpm.h:501:9: note: expected 'size_t {aka long unsigned int}' but argument is of type 'const char *'
    ssize_t tpm_getcap(struct tpm_chip *chip, u32 subcap_id, cap_t *cap,
            ^~~~~~~~~~

vim +/tpm_getcap +561 drivers/char/tpm/tpm_tis_core.c

41a5e1cf1 Christophe Ricard 2016-05-19  545  	if (rc < 0)
41a5e1cf1 Christophe Ricard 2016-05-19  546  		return IRQ_NONE;
41a5e1cf1 Christophe Ricard 2016-05-19  547  
41a5e1cf1 Christophe Ricard 2016-05-19  548  	tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &interrupt);
41a5e1cf1 Christophe Ricard 2016-05-19  549  	return IRQ_HANDLED;
41a5e1cf1 Christophe Ricard 2016-05-19  550  }
41a5e1cf1 Christophe Ricard 2016-05-19  551  
eb5854e76 Jarkko Sakkinen   2016-06-12  552  static int tpm_tis_gen_interrupt(struct tpm_chip *chip)
eb5854e76 Jarkko Sakkinen   2016-06-12  553  {
eb5854e76 Jarkko Sakkinen   2016-06-12  554  	const char *desc = "attempting to generate an interrupt";
eb5854e76 Jarkko Sakkinen   2016-06-12  555  	u32 cap2;
eb5854e76 Jarkko Sakkinen   2016-06-12  556  	cap_t cap;
eb5854e76 Jarkko Sakkinen   2016-06-12  557  
eb5854e76 Jarkko Sakkinen   2016-06-12  558  	if (chip->flags & TPM_CHIP_FLAG_TPM2)
eb5854e76 Jarkko Sakkinen   2016-06-12  559  		return tpm2_get_tpm_pt(chip, 0x100, &cap2, desc);
eb5854e76 Jarkko Sakkinen   2016-06-12  560  	else
c659af78e Stefan Berger     2017-01-19 @561  		return tpm_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap, desc,
c659af78e Stefan Berger     2017-01-19  562  				  0);
eb5854e76 Jarkko Sakkinen   2016-06-12  563  }
eb5854e76 Jarkko Sakkinen   2016-06-12  564  
41a5e1cf1 Christophe Ricard 2016-05-19  565  /* Register the IRQ and issue a command that will cause an interrupt. If an
41a5e1cf1 Christophe Ricard 2016-05-19  566   * irq is seen then leave the chip setup for IRQ operation, otherwise reverse
41a5e1cf1 Christophe Ricard 2016-05-19  567   * everything and leave in polling mode. Returns 0 on success.
41a5e1cf1 Christophe Ricard 2016-05-19  568   */
41a5e1cf1 Christophe Ricard 2016-05-19  569  static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask,

:::::: The code at line 561 was first introduced by commit
:::::: c659af78eb7b7d7be40f23d9d97bde58eb1368ac tpm: Check size of response before accessing data

:::::: TO: Stefan Berger <stefanb@...ux.vnet.ibm.com>
:::::: CC: Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
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