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Message-ID: <1486676048.14478.4.camel@intel.com>
Date: Thu, 9 Feb 2017 21:34:10 +0000
From: "De Marchi, Lucas" <lucas.demarchi@...el.com>
To: "mika.westerberg@...ux.intel.com" <mika.westerberg@...ux.intel.com>,
"andriy.shevchenko@...ux.intel.com"
<andriy.shevchenko@...ux.intel.com>,
"jarkko.nikula@...ux.intel.com" <jarkko.nikula@...ux.intel.com>,
"Nehal-Bakulchandra.Shah@....com" <Nehal-Bakulchandra.Shah@....com>
CC: "wsa@...-dreams.de" <wsa@...-dreams.de>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"suravee.suthikulpanit@....com" <suravee.suthikulpanit@....com>,
"linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>,
"Shyam-sundar.S-k@....com" <Shyam-sundar.S-k@....com>
Subject: Re: [PATCH] i2c: designware: Fix regression when dynamic TAR update
is disabled
On Thu, 2017-02-09 at 22:07 +0200, Andy Shevchenko wrote:
> On Fri, 2017-02-10 at 01:20 +0530, Shah Nehal-Bakulchandra wrote:
> > The following commit causes a regression when dynamic TAR update is
> > disabled:
> >
> > commit 63d0f0a6952a1a02bc4f116b7da7c7887e46efa3 ("i2c:
> > designware:
> > detect when dynamic tar update is possible")
>
> Please, leave just 12 characters, it still enough.
>
> > In such case, the DW_IC_CON_10BITADDR_MASTER is R/W, and is changed
> > by the logic that's trying to detect dynamic TAR update.The original
> > value of DW_IC_CON_10BITADDR_MASTER bit should be restored.
You are right, thanks for the fix. This may also explains why
0317e6c (i2c: designware: do not disable adapter after transfer) caused problems
and ended up being reverted. Could you try that on your hardware?
The dynamic tar update detection was only done as preparation work to allow not
disabling the adapter, which is reverted. We may also just revert this commit
instead of fixing the logic.
thanks
Lucas De Marchi
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