linux-kernel - Re: [PATCH 1/1] dma: imx-sdma: add 1ms delay to ensure SDMA channel is stopped

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Message-ID: <e1cd4749-7c66-b918-abc5-7f9e24cd2ff0@mentor.com>
Date:   Mon, 13 Feb 2017 15:30:19 +0900
From:   Jiada Wang <jiada_wang@...tor.com>
To:     Vinod Koul <vinod.koul@...el.com>
CC:     <dan.j.williams@...el.com>, <dmaengine@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/1] dma: imx-sdma: add 1ms delay to ensure SDMA channel
 is stopped

Hello Vinod

On 02/13/2017 11:05 AM, Vinod Koul wrote:
> On Fri, Feb 10, 2017 at 06:46:45AM -0800, jiada_wang@...tor.com wrote:
>> From: Jiada Wang <jiada_wang@...tor.com>
>>
>> sdma_disable_channel() cannot ensure dma is stopped to access
>> module's FIFOs. Maybe SDMA core is running and accessing BD when
>> disable of corresponding channel, this may cause sometimes even
>> after call of .sdma_disable_channel(), SDMA core still be running
>> and accessing module's FIFOs.
>>
>> We should add delay of one BD SDMA cost time, the maximum is 1ms.
>> So that SDMA clients by calling .device_terminate_all can
>> ensure SDMA core has really been stopped.
>>
>> Signed-off-by: Jiada Wang <jiada_wang@...tor.com>
>> ---
>>  drivers/dma/imx-sdma.c | 10 +++++++++-
>>  1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
>> index d1651a5..7332c40 100644
>> --- a/drivers/dma/imx-sdma.c
>> +++ b/drivers/dma/imx-sdma.c
>> @@ -937,6 +937,14 @@ static int sdma_disable_channel(struct dma_chan *chan)
>>  	return 0;
>>  }
>>
>> +static int sdma_disable_channel_with_delay(struct dma_chan *chan)
>> +{
>> +	sdma_disable_channel(chan);
>> +	mdelay(1);
>
> what is the gaurantee that 1ms is fine? Shouldn't you poll the bit to see
> channel is disabled properly..
>
I got the information from NXP (freescale) R&D team,
according to them, by write '1' to SDMA_H_STATSTOP, only disables
the related sdma channel (so poll HE bit will indicates the channel has 
been disabled),
but it cannot ensure SDMA core stop to access modules' FIFO,
SDMA core may still is running, this is a bug in HW.

regarding if the '1ms' is enough to ensure SDMA core has stopped,
NXP R&D team mentioned:
"we should add some delay of one BD SDMA cost time after disable the 
channel bit, the maximum is 1ms"
so I assume 1ms should work for all cases

Thanks,
Jiada
>> +
>> +	return 0;
>> +}
>> +
>>  static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
>>  {
>>  	struct sdma_engine *sdma = sdmac->sdma;
>> @@ -1828,7 +1836,7 @@ static int sdma_probe(struct platform_device *pdev)
>>  	sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
>>  	sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
>>  	sdma->dma_device.device_config = sdma_config;
>> -	sdma->dma_device.device_terminate_all = sdma_disable_channel;
>> +	sdma->dma_device.device_terminate_all = sdma_disable_channel_with_delay;
>>  	sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
>>  	sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
>>  	sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
>> --
>> 2.7.4
>>
>>
>