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Date:   Thu, 16 Feb 2017 14:47:07 -0800 (PST)
To:     Moritz Fischer <>
cc:     Alan Tull <>,,
        Linux Kernel Mailing List <>,
        Devicetree List <>,
        Rob Herring <>,
        Mark Rutland <>
Subject: Re: [PATCH 2/4] fpga pr ip: Core driver support for Altera Partial
 Reconfiguration IP.

Hi Moritz,

Thanks for the feedback.

On Thu, 16 Feb 2017, Moritz Fischer wrote:

> Hi Matthew,
> On Wed, Feb 15, 2017 at 1:10 PM,  <> wrote:
>> +static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
>> +                                     struct fpga_image_info *info)
>> +{
>> +       u32 i;
>> +
>> +       for (i = 0; i < info->config_complete_timeout_us; i++) {
>> +               switch (alt_pr_fpga_state(mgr)) {
>> +               case FPGA_MGR_STATE_WRITE_ERR:
>> +                       return -EIO;
>> +
>> +               case FPGA_MGR_STATE_OPERATING:
>> +                       dev_info(&mgr->dev,
>> +                                "successful partial reconfiguration\n");
>> +                       return 0;
>> +
>> +               default:
>> +                       break;
>> +               }
>> +               udelay(1);
> Does this need to be a udelay? would a usleep_range() do maybe?

The actual timeout required is design specific.  The member,
config_complete_timeout_us, is defined in microseconds, and my experience 
is that a small number of microseconds (e.g. < 10) is usually plenty. 
Other FPGAs and designs might be different.  My quick reading of kernel 
timers says usleep_range() is good for 10 us - 20 ms.  In this driver, if 
usleep_range(1) can put less pressure on the CPU and schedular at the cost 
of little accuracy, I will be happy to switch, but at this time I don't 
know if usleep_range() would be better or not.

> Could we maybe pull the timeout part into the framework if all drivers are doing
> is to wait / poll for the state to be a certain value?

I think it is safe to say that all variations of FPGAs need some amount of 
time after the bitstream to be delivered before the FPGA is "ready".  If 
that time is exceeded then the fpga programming has failed.  If all FPGA 
variations are doing a poll for some amount of time, then it would be good 
to move the polling up to the framework.  I think such a change would be 
better in its own patch set.

> Thanks,
> Moritz
> --
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