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Date: Fri, 17 Feb 2017 14:55:01 +0100 From: Thomas Petazzoni <thomas.petazzoni@...e-electrons.com> To: Gregory CLEMENT <gregory.clement@...e-electrons.com> Cc: Jisheng Zhang <jszhang@...vell.com>, <davem@...emloft.net>, <arnd@...db.de>, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org Subject: Re: [PATCH net-next v2 2/2] net: mvneta: Use cacheable memory to store the rx buffer DMA address Hello, On Fri, 17 Feb 2017 14:30:03 +0100, Gregory CLEMENT wrote: > I have just tested it and as I feared, with HWBM enabled, a simple iperf > just doesn't work. And that's expected: the whole point of HWBM is that the buffer into which a RX packet is placed is allocated by the HW, and its address stored in the RX descriptor. So the following code: > > rx_desc->buf_phys_addr = phys_addr; > > i = rx_desc - rxq->descs; > > + rxq->buf_dma_addr[i] = phys_addr; Does not make sense, because it's not the SW that refills the RX descriptors with the address of the RX buffers. It's done by the HW. With HWBM, I believe you have no choice but to read the physical address from the RX descriptor. But you can probably optimize things a little bit by reading it only once, and then storing it into a cacheable variable. So maybe: - For SWBM, use the strategy proposed by Jisheng - For HWBM, at the beginning of the RX completion path, read once the rx_desc->buf_phys_addr, and store it in rxq->buf_dma_addr[index] Of course that's just a very rough proposal. I've been looking mainly at mvpp2 lately, and I'm not sure I still remember how mvneta works in the details. Best regards, Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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