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Message-ID: <890292613.23897064.1487628173163.JavaMail.zimbra@redhat.com>
Date: Mon, 20 Feb 2017 17:02:53 -0500 (EST)
From: Paolo Bonzini <pbonzini@...hat.com>
To: Andy Lutomirski <luto@...capital.net>
Cc: kvm list <kvm@...r.kernel.org>, linux-kernel@...r.kernel.org,
X86 ML <x86@...nel.org>, "H. Peter Anvin" <hpa@...or.com>,
Borislav Petkov <bpetkov@...e.de>
Subject: Re: RFC: Getting rid of LTR in VMX
> > Yes. But 150-200 clock cycles are nothing compared to the cache misses
> > you get from preemption, so I'd ignore that. Saving 300 clock cycles on
> > userspace exits from TR+GSBASE would be about 5% on my Haswell.
>
> That's still 5% :)
Yes, 5% on userspace exits is good (though they're rare).
OTOH, 300 clock cycles on preemption are nothing to write home about.
Paolo
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