[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <3908561D78D1C84285E8C5FCA982C28F3A2BE9B1@ORSMSX114.amr.corp.intel.com>
Date: Tue, 21 Feb 2017 18:20:19 +0000
From: "Luck, Tony" <tony.luck@...el.com>
To: "xlpang@...hat.com" <xlpang@...hat.com>,
Borislav Petkov <bp@...en8.de>
CC: Prarit Bhargava <prarit@...hat.com>,
Kiyoshi Ueda <k-ueda@...jp.nec.com>,
Peter Zijlstra <peterz@...radead.org>,
"x86@...nel.org" <x86@...nel.org>,
"kexec@...ts.infradead.org" <kexec@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Ingo Molnar <mingo@...hat.com>,
Junichi Nomura <j-nomura@...jp.nec.com>,
Naoya Horiguchi <n-horiguchi@...jp.nec.com>,
Dave Young <dyoung@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>
Subject: RE: [PATCH] x86/mce: Keep quiet in case of broadcasted mce after
system panic
> It's from my understanding, I didn't get the explicit description from the intel SDM on this point.
> If a broadcast SRAO comes on real hardware, will MSR_IA32_MCG_STATUS of each cpu have MCG_STATUS_RIPV bit set?
MCG_STATUS is a per-thread MSR and will contain the status appropriate for that thread when #MC is delivered.
So the RIPV bit will be set if, and only if, the thread saved a valid return address for this exception. The net result
is that it is almost always set for "innocent bystander" CPUs that were dragged into the exception handler because
of a broadcast #MC. We make the test because if it isn't set, then the do_machine_check() had better not return
because we have no idea where it will return to - since there is not a valid return IP.
-Tony
Powered by blists - more mailing lists