lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20170228174205.GE30601@mai>
Date:   Tue, 28 Feb 2017 18:42:05 +0100
From:   Daniel Lezcano <daniel.lezcano@...aro.org>
To:     Andreas Färber <afaerber@...e.de>
Cc:     arm@...nel.org, support@...aker.org, linux-kernel@...r.kernel.org,
        mp-cs@...ions-semi.com, 96boards@...obotics.com,
        Thomas Gleixner <tglx@...utronix.de>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v3 05/25] clocksource: owl: Add S900 support

On Tue, Feb 28, 2017 at 06:16:10PM +0100, Andreas Färber wrote:
> Daniel,
> 
> Am 28.02.2017 um 07:35 schrieb Andreas Färber:
> > The Actions Semi S900 SoC provides four 32-bit timers, TIMER0/1/2/3,
> > but no 2Hz timers.
> > 
> > Deal with the S500 having less timers.
> > 
> > An S900 datasheet can be found in 96Boards documentation:
> > https://github.com/96boards/documentation/blob/master/ConsumerEdition/Bubblegum-96/HardwareDocs/SoC_bubblegum96.pdf
> > 
> > Signed-off-by: Andreas Färber <afaerber@...e.de>
> [...]
> > @@ -126,10 +127,20 @@ static irqreturn_t owl_timer1_interrupt(int irq, void *dev_id)
> >  static const struct owl_timer_info s500_timer_info = {
> >  	.timer_offset[0] = 0x08,
> >  	.timer_offset[1] = 0x14,
> > +	.timer_offset[2] = -1,
> > +	.timer_offset[3] = -1,
> > +};
> > +
> > +static const struct owl_timer_info s900_timer_info = {
> > +	.timer_offset[0] = 0x08,
> > +	.timer_offset[1] = 0x14,
> > +	.timer_offset[2] = 0x30,
> > +	.timer_offset[3] = 0x3c,
> >  };
> 
> I noticed later that the S900 manual describes TIMER2/3 as "used only in
> Secure mode". My driver code resetting them seems to work though.
> 
> Should we just drop these extra timer initializations then to make the
> driver simpler and more performant again? I'd still like to keep the two
> compatible strings in the DT though, and we may want to disable the 2Hz
> timers on S500 just in case.

Yes, makes sense.

> -- 
> SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Felix Imendörffer, Jane Smithard, Graham Norton
> HRB 21284 (AG Nürnberg)

-- 

 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ