linux-kernel - Re: [PATCH v2 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 22 Mar 2017 12:06:46 +0100
From:   Heiko Stübner <heiko@...ech.de>
To:     Elaine Zhang <zhangqing@...k-chips.com>
Cc:     cl@...k-chips.com, robh+dt@...nel.org, mark.rutland@....com,
        zhengxing@...k-chips.com, andy.yan@...k-chips.com,
        jay.xu@...k-chips.com, matthias.bgg@...il.com,
        paweljarosz3691@...il.com, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        wsa@...-dreams.de, linux-i2c@...r.kernel.org, jic23@...nel.org,
        knaack.h@....de, lars@...afoo.de, pmeerw@...erw.net,
        wxt@...k-chips.com, david.wu@...k-chips.com,
        linux-iio@...r.kernel.org, shawn.lin@...k-chips.com,
        akpm@...ux-foundation.org, dianders@...omium.org,
        yamada.masahiro@...ionext.com, catalin.marinas@....com,
        will.deacon@....com, afaerber@...e.de, shawnguo@...nel.org,
        khilman@...libre.com, arnd@...db.de, fabio.estevam@....com,
        kever.yang@...k-chips.com, tony.xie@...k-chips.com,
        huangtao@...k-chips.com, yhx@...k-chips.com,
        rocky.hao@...k-chips.com
Subject: Re: [PATCH v2 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs

Am Mittwoch, 22. März 2017, 18:23:56 CET schrieb Elaine Zhang:
> On 03/21/2017 04:55 PM, Heiko Stübner wrote:
> > Am Donnerstag, 16. März 2017, 21:17:22 CET schrieb cl@...k-chips.com:
> >> +	cru: clock-controller@...40000 {
> >> +		compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
> >> +		reg = <0x0 0xff440000 0x0 0x1000>;
> >> +		rockchip,grf = <&grf>;
> >> +		#clock-cells = <1>;
> >> +		#reset-cells = <1>;
> >> +		assigned-clocks =
> >> +			<&cru DCLK_LCDC>, <&cru SCLK_PDM>,
> >> +			<&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
> >> +			<&cru SCLK_UART1>, <&cru SCLK_UART2>,
> >> +			<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
> >> +			<&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
> >> +			<&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
> >> +			<&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
> >> +			<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
> >> +			<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
> >> +			<&cru SCLK_SDIO>, <&cru SCLK_TSP>,
> >> +			<&cru SCLK_WIFI>, <&cru ARMCLK>,
> >> +			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
> >> +			<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
> >> +			<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
> >> +			<&cru HCLK_PERI>, <&cru PCLK_PERI>,
> >> +			<&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
> >> +			<&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
> >> +			<&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
> >> +			<&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
> >> +			<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
> >> +			<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
> >> +			<&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
> >> +			<&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
> >> +			<&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
> > 
> > that list is way to long.
> > Device-specific clocks should be inited in their respective device nodes.
> 
> Cpll init freq is 1200M, is too high. we need set cpll child clk div
> first,and then set cpll freq.
> After pll init, others clk init freq can inited in their device node.

thanks, that is a nice explanation. Please put it into a comment above the 
assigned-clocks property, so that we can keep that knowledge around for later 
times :-) .


Thanks
Heiko