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Message-ID: <CANk1AXTb=b8urUJ-Nc7hVOT03HTt=Thtb5HiufdjQHuWd1NsYw@mail.gmail.com>
Date:   Wed, 22 Mar 2017 10:28:34 -0500
From:   Alan Tull <delicious.quinoa@...il.com>
To:     matthew.gerlach@...ux.intel.com
Cc:     Moritz Fischer <moritz.fischer@...us.com>,
        linux-fpga@...r.kernel.org,
        linux-kernel <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Anatolij Gustschin <agust@...x.de>
Subject: Re: [PATCH v6 2/4] fpga pr ip: Core driver support for Altera Partial
 Reconfiguration IP.

On Tue, Mar 21, 2017 at 4:02 PM,  <matthew.gerlach@...ux.intel.com> wrote:
> From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>
> Adding the core functions necessary for a fpga-mgr driver
> for the Altera Partial IP component.  It is intended for
> these functions to be used by the various bus implementations
> like the platform bus or the PCIe bus.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>

Acked-by: Alan Tull <atull@...nel.org>

> ---
> v6:
>     Suggestions from Anatolij Gustschin <agust@...x.de>
>     s/pr_err/dev_err/g
>     Change for loop to do/while to handle config_complete_timeout_us == 0
>     move altera-pr-ip-core.h to include/linux/fpga
> v5:
>     Fix comment as suggested by Rob Herring <robh@...nel.org>
> v4:
>     v3 patch set mistakenly sent out labeled as v4
> v3:
>     s/alt_pr_probe/alt_pr_register/
>     s/alt_pr_remove/alt_pr_unregister/
>

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