linux-kernel - RE: [PATCH v2 0/7] Renesas RZ/A1 pin and gpio controller

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Message-ID: <SG2PR06MB1165AB3D48DA3450FC27EA3D8A3C0@SG2PR06MB1165.apcprd06.prod.outlook.com>
Date:   Wed, 22 Mar 2017 18:10:26 +0000
From:   Chris Brandt <Chris.Brandt@...esas.com>
To:     Jacopo Mondi <jacopo+renesas@...ndi.org>,
        "geert+renesas@...der.be" <geert+renesas@...der.be>,
        "laurent.pinchart@...asonboard.com" 
        <laurent.pinchart@...asonboard.com>,
        "linus.walleij@...aro.org" <linus.walleij@...aro.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>
CC:     "linux-renesas-soc@...r.kernel.org" 
        <linux-renesas-soc@...r.kernel.org>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 0/7] Renesas RZ/A1 pin and gpio controller

Hi Jacopo,

On Monday, March 20, 2017, Jacopo Mondi wrote:
> Chris: it would be great if you could give this another spin on RSK board.


I tested these patches on an RZ/A1H RSK board after modifying the DT for
the RSK vs the GENMAI board.

The following worked fine:
 * SCIF
 * I2C
 * SDHI
 * Ethernet

I see Geert has already responded with mostly text (grammar) changes.
As for the "API" of the driver from a user perspective, I think it should
cover all the use cases of the peripherals.


For your reference, here was my pin config for the RSK board testing. Once
this driver is (hopefully) accepted, I will update the upstream rskrza1 DT. 


--- RSK BOARD PIN SETUP ---

&pinctrl {

	scif2_pins: serial2 {
		/* P3_0 as TxD2; P3_2 as RxD2 */
		renesas,pins = <PIN(3, 0) 6>,
			       <PIN(3, 2) 4>;
	};

	/* RIIC Ch 3 */
	i2c3_pins: i2c3 {
		/* RIIC3: P1_6 as SCL, P1_7 as SDA */
		renesas,pins = <PIN(1, 6) (1 | BI_DIR)>,
			       <PIN(1, 7) (1 | BI_DIR)>;
	};

	/* SHDI ch1 on CN1 */
	sdhi1_pins: sdhi1 {
		/* SHDI ch1 on Port 3 */
		renesas,pins = <PIN(3, 8) (7)>,		/* SDHI1 CD */
				<PIN(3, 9) (7)>,		/* SDHI1 WP */
				<PIN(3, 10) (7 | BI_DIR)>,	/* SDHI1 DAT1 */
				<PIN(3, 11) (7 | BI_DIR)>,	/* SDHI1 DAT0 */
				<PIN(3, 12) (7)>,		/* SDHI1 CLK */
				<PIN(3, 13) (7 | BI_DIR)>,	/* SDHI1 CMD */
				<PIN(3, 14) (7 | BI_DIR)>,	/* SDHI1 DAT3 */
				<PIN(3, 15) (7 | BI_DIR)>;	/* SDHI1 DAT2 */
	};

	/* Ethernet */
	ether_pins: ether {
		/* Ethernet on Ports 1,2,3,5 */
		renesas,pins = <PIN(1, 14) (4)>, /* P1_14 = ET_COL */
			<PIN(5, 9) (2)>,	/* P5_9 = ET_MDC */
			<PIN(3, 3) (2 | BI_DIR)>,	/* P3_3 = ET_MDIO (bi dir) */
			<PIN(3, 4) (2)>,	/* P3_4 = ET_RXCLK */
			<PIN(3, 5) (2)>,	/* P3_5 = ET_RXER */
			<PIN(3, 6) (2)>,	/* P3_6 = ET_RXDV */
			<PIN(2, 0) (2)>,	/* P2_0 = ET_TXCLK */
			<PIN(2, 1) (2)>,	/* P2_1 = ET_TXER */
			<PIN(2, 2) (2)>,	/* P2_2 = ET_TXEN */
			<PIN(2, 3) (2)>,	/* P2_3 = ET_CRS */
			<PIN(2, 4) (2)>,	/* P2_4 = ET_TXD0 */
			<PIN(2, 5) (2)>,	/* P2_5 = ET_TXD1 */
			<PIN(2, 6) (2)>,	/* P2_6 = ET_TXD2 */
			<PIN(2, 7) (2)>,	/* P2_7 = ET_TXD3 */
			<PIN(2, 8) (2)>,	/* P2_8 = ET_RXD0 */
			<PIN(2, 9) (2)>,	/* P2_9 = ET_RXD1 */
			<PIN(2, 10) (2)>, /* P2_10 = ET_RXD2 */
			<PIN(2, 11) (2)>; /* P2_11 = ET_RXD3 */
	};
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;
};

&scif2 {
	pinctrl-names = "default";
	pinctrl-0 = <&scif2_pins>;
};

&sdhi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sdhi1_pins>;
};

&ether {
	pinctrl-names = "default";
	pinctrl-0 = <&ether_pins>;
};

/ {
	leds {
		status = "okay";
		compatible = "gpio-leds";

		led1 {
			gpios = <&port7 1 GPIO_ACTIVE_LOW>;
		};
	};
};



Thank you,
Chris