linux-kernel - RE: [PATCH V3 2/2] perf/x86: add sysfs entry to freeze counter on SMI

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077536C61D3@SHSMSX103.ccr.corp.intel.com>
Date:   Tue, 28 Mar 2017 13:23:00 +0000
From:   "Liang, Kan" <kan.liang@...el.com>
To:     Thomas Gleixner <tglx@...utronix.de>
CC:     "peterz@...radead.org" <peterz@...radead.org>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "bp@...en8.de" <bp@...en8.de>, "acme@...nel.org" <acme@...nel.org>,
        "eranian@...gle.com" <eranian@...gle.com>,
        "jolsa@...nel.org" <jolsa@...nel.org>,
        "ak@...ux.intel.com" <ak@...ux.intel.com>
Subject: RE: [PATCH V3 2/2] perf/x86: add sysfs entry to freeze counter on
 SMI



> 
> On Mon, 27 Mar 2017, kan.liang@...el.com wrote:
> > +
> > +	if (val)
> > +		msr_set_bit_on_cpus(cpu_possible_mask,
> MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
> > +	else
> > +		msr_clear_bit_on_cpus(cpu_possible_mask,
> MSR_IA32_DEBUGCTLMSR,
> > +DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
> 
> This is still not protected against CPU hotplug. What's so hard about:
> 
> 	get_online_cpus();
> 
> 	if (val) {
> 		msr_set_bit_on_cpus(cpu_online_mask,
> MSR_IA32_DEBUGCTLMSR,
> 				    DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
> 	} else {
> 		msr_clear_bit_on_cpus(cpu_online_mask,
> MSR_IA32_DEBUGCTLMSR,
> 
> DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
> 	}
> 
> 	put_online_cpus();
> 
> Aside of that, when this is set to SMI freeze, what causes a CPU which
> comes online after that point to set the bit as well? Nothing AFAICT.
> 
> 

I've patched the intel_pmu_cpu_starting.
I think it guarantees that the new online CPU is set.

@@ -3174,6 +3174,11 @@ static void intel_pmu_cpu_starting(int cpu)
 
 	cpuc->lbr_sel = NULL;
 
+	if (x86_pmu.attr_freeze_on_smi)
+		msr_set_bit_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
+	else
+		msr_clear_bit_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
+
 	if (!cpuc->shared_regs)
 		return;

Thanks,
Kan