linux-kernel - Re: [alsa-devel][PATCH v2 2/2] ASoC: wm8960: Let wm8960 driver configure its bit clock and frame clock

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Message-ID: <20170403133434.GU6986@localhost.localdomain>
Date:   Mon, 3 Apr 2017 14:34:34 +0100
From:   Charles Keepax <ckeepax@...nsource.wolfsonmicro.com>
To:     Daniel Baluta <daniel.baluta@...il.com>
CC:     Zidan Wang <b50113@...escale.com>, Mark Brown <broonie@...nel.org>,
        Zidan Wang <zidan.wang@...escale.com>,
        Liam Girdwood <lgirdwood@...il.com>,
        Jaroslav Kysela <perex@...ex.cz>, <tiwai@...e.de>,
        Lars-Peter Clausen <lars@...afoo.de>,
        <patches@...nsource.wolfsonmicro.com>,
        <alsa-devel@...a-project.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        <shengjiu.wang@....com>, <mihai.serban@....com>,
        <viorel.suman@....com>
Subject: Re: [alsa-devel][PATCH v2 2/2] ASoC: wm8960: Let wm8960 driver
 configure its bit clock and frame clock

On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
> On Thu, Jan 15, 2015 at 3:34 PM, Zidan Wang <b50113@...escale.com> wrote:
> > On Wed, Jan 14, 2015 at 07:27:03PM +0000, Mark Brown wrote:
> >> On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote:
> > I found it can't generate bclk for S20_3LE data format.
> >
> > For 2 channel S20_3LE data format:
> >
> > bclk = fs * 20 * 2
> > Sysclk = BCLKDIV * bclk = BCLKDIV * fs * 40
> > Sysclk = DACDIV * fs * 256
> >
> > BCLKDIV/DACDIV = 256/40 = 32/5
> >
> > But BCLKDIV/DACDIV can't be 32/5. So I want to support tdm slot.
> >
> > bclk = fs * slot_width * slots * channal.
> >
> > Do you think it make sense, or any other ideas?
> 
> Reviving this question after two years :).
> 
> After "ASoC: codec: wm8960: Relax bit clock computation" patch
> 
> https://patchwork.kernel.org/patch/9636769/
> 
> we can now support S20_3LE for round rates like 8000, 16000,
> 32000 and 48000.
> 
> But not for 11025, 22050, 441000. Do you think it's worth exploring
> "tdm slot" idea? I don't know exactly what it implies.
> 
> Another idea, is to completely remove support for S20_3LE since it
> is not trivial to derive bitclk from sysclk.
> 
> What do you guys think?

Does this problem still remain after the relaxed clock
computation? The maths you quote depends on the derived BCLK
being exactly the correct speed for the audio, that is no longer
the case anymore.

I would have thought the patch would cover both situations, as in
if we can produce a suitable LRCLK, then we just pick a BCLK we
can produce that is higher than we need. I don't see why that
depends on things being a 48k based rate there. Am I missing
something?

Thanks,
Charles