linux-kernel - Re: [PATCH v4 1/5] platform/x86: intel_pmc

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 4 Apr 2017 16:25:25 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@...il.com>
Cc:     Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>,
        Andy Shevchenko <andy@...radead.org>,
        Zha Qipeng <qipeng.zha@...el.com>,
        "dvhart@...radead.org" <dvhart@...radead.org>,
        Guenter Roeck <linux@...ck-us.net>,
        Wim Van Sebroeck <wim@...ana.be>,
        David Box <david.e.box@...ux.intel.com>,
        Rajneesh Bhardwaj <rajneesh.bhardwaj@...el.com>,
        Platform Driver <platform-driver-x86@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-watchdog@...r.kernel.org
Subject: Re: [PATCH v4 1/5] platform/x86: intel_pmc_ipc: fix gcr offset

Please, STOP top-posting.

On Mon, Apr 3, 2017 at 4:51 AM, Sathyanarayanan Kuppuswamy Natarajan
<sathyaosid@...il.com> wrote:
> Yes, just applying this patch will fix the existing offset issue.

Then the question how it was tested in both cases (before this change and now) ?

>
> On Sun, Apr 2, 2017 at 7:11 AM, Andy Shevchenko
> <andy.shevchenko@...il.com> wrote:
>> On Sat, Apr 1, 2017 at 2:27 AM, Kuppuswamy Sathyanarayanan
>> <sathyanarayanan.kuppuswamy@...ux.intel.com> wrote:
>>> According to Broxton APL PMC spec, gcr mem region starts
>>> at offset 0x1000 from ipc mem base address. In this driver,
>>> PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR
>>> memory region from IPC mem region. So we should use 0x1000(4K)
>>> as GCR offset. But currently this driver uses 0x1008 as GCT
>>> offset.This patch fixes this issue.
>>
>>
>> So, if I apply this one independently, would it fix an existin issue?
>>
>>>
>>> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@...ux.intel.com>
>>> ---
>>>  drivers/platform/x86/intel_pmc_ipc.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> Changes since v3:
>>>  * Updated the commit history
>>>
>>> diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c
>>> index 0651d47..0a33592 100644
>>> --- a/drivers/platform/x86/intel_pmc_ipc.c
>>> +++ b/drivers/platform/x86/intel_pmc_ipc.c
>>> @@ -82,7 +82,7 @@
>>>  /* exported resources from IFWI */
>>>  #define PLAT_RESOURCE_IPC_INDEX                0
>>>  #define PLAT_RESOURCE_IPC_SIZE         0x1000
>>> -#define PLAT_RESOURCE_GCR_OFFSET       0x1008
>>> +#define PLAT_RESOURCE_GCR_OFFSET       0x1000
>>>  #define PLAT_RESOURCE_GCR_SIZE         0x1000
>>>  #define PLAT_RESOURCE_BIOS_DATA_INDEX  1
>>>  #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
>>> --
>>> 2.7.4
>>>
>>
>>
>>
>> --
>> With Best Regards,
>> Andy Shevchenko
>
>
>
> --
> --
>
> Sathya



-- 
With Best Regards,
Andy Shevchenko