lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAENHMvO7KYFcEvGeCnA9bBYC3qTn7o8f1B6-maS5Z6n_d1Z=DQ@mail.gmail.com>
Date:   Wed, 12 Apr 2017 10:59:19 -0700
From:   Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@...il.com>
To:     Lee Jones <lee.jones@...aro.org>
Cc:     Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>, gnurou@...il.com,
        linus.walleij@...aro.org, edubezval@...il.com,
        dvhart@...radead.org, rui.zhang@...el.com,
        Andy Shevchenko <andy@...radead.org>,
        Hans de Goede <hdegoede@...hat.com>,
        linux-gpio@...r.kernel.org,
        Platform Driver <platform-driver-x86@...r.kernel.org>,
        linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org
Subject: Re: [PATCH v1 1/7] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index

Hi Lee,

Thanks. Will remove the code segment in next version.

On Wed, Apr 12, 2017 at 3:45 AM, Lee Jones <lee.jones@...aro.org> wrote:
> On Mon, 10 Apr 2017, sathyanarayanan.kuppuswamy@...ux.intel.com wrote:
>
>> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@...ux.intel.com>
>>
>> TMU interrupts are registered as a separate interrupt chip, and
>> hence it should start its interrupt index(BXTWC_TMU_IRQ) number
>> from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum
>> bxtwc_irqs_level2 and its index value is 11. Since this index
>> value is used when calculating .num_irqs of regmap_irq_chip_tmu,
>> it incorrectly reports number of irqs as 12 instead of actual
>> value of 1.
>>
>> static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
>>       REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
>> };
>>
>> static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
>>       .name = "bxtwc_irq_chip_tmu",
>>       .status_base = BXTWC_TMUIRQ,
>>       .mask_base = BXTWC_MTMUIRQ,
>>       .irqs = bxtwc_regmap_irqs_tmu,
>>       .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
>>       .num_regs = 1,
>> };
>>
>> This patch fixes this issue by creating new enum of tmu irqs and
>> resetting its starting index to 0.
>>
>> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@...ux.intel.com>
>> ---
>>  drivers/mfd/intel_soc_pmic_bxtwc.c | 5 ++++-
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> Patch looks fine, but please remove the code segment from the commit
> log.
>
> For the code:
>
> For my own reference:
>   Acked-for-MFD-by: Lee Jones <lee.jones@...aro.org>
>
>> diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
>> index 699c8c7..bb18e20 100644
>> --- a/drivers/mfd/intel_soc_pmic_bxtwc.c
>> +++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
>> @@ -94,7 +94,10 @@ enum bxtwc_irqs_level2 {
>>       BXTWC_GPIO0_IRQ,
>>       BXTWC_GPIO1_IRQ,
>>       BXTWC_CRIT_IRQ,
>> -     BXTWC_TMU_IRQ,
>> +};
>> +
>> +enum bxtwc_irqs_tmu {
>> +     BXTWC_TMU_IRQ = 0,
>>  };
>>
>>  static const struct regmap_irq bxtwc_regmap_irqs[] = {
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog



-- 
Sathya

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ