linux-kernel - [PATCH v2 10/30] arm: dts: mt7623: add spi nodes to the mt7623.dtsi file

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Message-ID: <1493198774-4478-11-git-send-email-sean.wang@mediatek.com>
Date:   Wed, 26 Apr 2017 17:25:54 +0800
From:   <sean.wang@...iatek.com>
To:     <robh+dt@...nel.org>, <matthias.bgg@...il.com>, <john@...ozen.org>,
        <mark.rutland@....com>, <linux@...linux.org.uk>,
        <linus.walleij@...aro.org>, <devicetree@...r.kernel.org>,
        <linux-mediatek@...ts.infradead.org>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-gpio@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Sean Wang <sean.wang@...iatek.com>
Subject: [PATCH v2 10/30] arm: dts: mt7623: add spi nodes to the mt7623.dtsi file

From: Sean Wang <sean.wang@...iatek.com>

Add spi controller nodes to the mt7623.dtsi file

Signed-off-by: John Crispin <john@...ozen.org>
Signed-off-by: Sean Wang <sean.wang@...iatek.com>
---
 arch/arm/boot/dts/mt7623.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index adb4793..131808c 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -288,6 +288,48 @@
 		status = "disabled";
 	};
 
+	spi0: spi@...0a000 {
+		compatible = "mediatek,mt7623-spi",
+			     "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x1100a000 0 0x100>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI0_SEL>,
+			 <&pericfg CLK_PERI_SPI0>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
+	spi1: spi@...16000 {
+		compatible = "mediatek,mt7623-spi",
+			     "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x11016000 0 0x100>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI1_SEL>,
+			 <&pericfg CLK_PERI_SPI1>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
+	spi2: spi@...17000 {
+		compatible = "mediatek,mt7623-spi",
+			     "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x11017000 0 0x1000>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI2_SEL>,
+			 <&pericfg CLK_PERI_SPI2>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
 	hifsys: syscon@...00000 {
 		compatible = "mediatek,mt7623-hifsys",
 			     "mediatek,mt2701-hifsys",
-- 
1.9.1