linux-kernel - Re: [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

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Date:   Thu, 27 Apr 2017 22:07:34 +0530
From:   Sunil Kovvuri <sunil.kovvuri@...il.com>
To:     Robert Richter <robert.richter@...ium.com>
Cc:     Geetha sowjanya <gakula@...iumnetworks.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Catalin Marinas <catalin.marinas@....com>, jcm@...hat.com,
        linu.cherian@...ium.com, Will Deacon <will.deacon@....com>,
        LKML <linux-kernel@...r.kernel.org>,
        geethasowjanya.akula@...il.com, linux-acpi@...r.kernel.org,
        iommu@...ts.linux-foundation.org,
        Hanjun Guo <hanjun.guo@...aro.org>, sudeep.holla@....com,
        Geetha <gakula@...ium.com>, Sunil Goutham <sgoutham@...ium.com>,
        Robin Murphy <robin.murphy@....com>,
        LAKML <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

On Thu, Apr 27, 2017 at 7:09 PM, Robert Richter
<robert.richter@...ium.com> wrote:
> On 27.04.17 17:16:21, Geetha sowjanya wrote:
>> From: Geetha <gakula@...ium.com>
>>
>> Cavium CN99xx SMMUv3 implementation has two Silicon Erratas.
>> 1. Errata ID #74
>>    SMMU register alias Page 1 is not implemented
>> 2. Errata ID #126
>>    SMMU doesnt support unique IRQ lines for gerror, eventq and cmdq-sync
>>
>> The following patchset does software workaround for these two erratas.
>>
>> This series is based on RFC patch.
>> https://www.spinics.net/lists/arm-kernel/msg575739.html
>>
>> As suggested by Will Deacon, code is modified to use silicon id to
>> enable errata#74 workaround.
>
> Can we go with the previous series [1] and:
>
>  * drop the iort model numbering part,
>
>  * add an enablement function that enables flags (smmu->options)
>    depending on midr values (which replaces the macro code)?

I don't see how it is efficient and consistent, if we take data from DT
for non-ACPI mode and read CPU ID from MIDR for ACPI mode.

Thanks,
Sunil.

>
> E.g.:
>
> static void acpi_smmu_enable_cavium(struct arm_smmu_device *smmu)
> {
>         u32 cpu_model;
>
>         if (!IS_ENABLED(CONFIG_ARM64))
>                 return;
>
>         cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
>         switch (cpu_model) {
>         case ...:
>         case ...:
>                 break;
>         default:
>                 /* No Cavium CN99xx SMMU v3 */
>                 return;
>         }
>
>         smmu->options |= (ARM_SMMU_OPT_PAGE0_REGS_ONLY |
>                          ARM_SMMU_OPT_USE_SHARED_IRQS);
> }
>
> -Robert
>
>
> [1] [RFC PATCH 0/7] Cavium CN99xx SMMUv3 Errata workarounds
>     https://marc.info/?l=linux-acpi&m=149192179623708&w=2
>
>>
>> Linu Cherian (1):
>>   iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74
>>
>> Geetha (2):
>>   arm64: Add MIDR values for Cavium cn99xx SoCs
>>   iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
>>
>>  Documentation/arm64/silicon-errata.txt |  2 ++
>>  arch/arm64/include/asm/cputype.h       |  3 ++
>>  drivers/acpi/arm64/iort.c              | 14 +++++++-
>>  drivers/iommu/arm-smmu-v3.c            | 64 +++++++++++++++++++++++++++++-----
>>  4 files changed, 73 insertions(+), 10 deletions(-)
>>
>> --
>> 1.9.1
>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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