linux-kernel - Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20170427164237.GA7114@leverpostej>
Date:   Thu, 27 Apr 2017 17:42:37 +0100
From:   Mark Rutland <mark.rutland@....com>
To:     Geetha sowjanya <gakula@...iumnetworks.com>
Cc:     will.deacon@....com, robin.murphy@....com,
        lorenzo.pieralisi@....com, hanjun.guo@...aro.org,
        sudeep.holla@....com, iommu@...ts.linux-foundation.org,
        jcm@...hat.com, linu.cherian@...ium.com,
        linux-kernel@...r.kernel.org, geethasowjanya.akula@...il.com,
        linux-acpi@...r.kernel.org, robert.richter@...ium.com,
        catalin.marinas@....com, Geetha <gakula@...ium.com>,
        sgoutham@...ium.com, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium
 ThunderX2 erratum #74

On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
> +	/*
> +	 * Override the size, for Cavium CN99xx implementations
> +	 * which doesn't support the page 1 SMMU register space.
> +	 */
> +	cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
> +	if (cpu_model == MIDR_THUNDERX_99XX ||
> +	    cpu_model == MIDR_BRCM_VULCAN)
> +		size = SZ_64K;

If you're trying to identify an SMMU erratum, identify the SMMU, not the
CPU it happens to be paired with this time.

There are ID registers in the SMMU you can use to do so.

NAK to using the CPU ID here.

Mark.