linux-kernel - Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable

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Message-ID: <20170504074226.GR30730@tbergstrom-lnx.Nvidia.com>
Date:   Thu, 4 May 2017 10:42:26 +0300
From:   Peter De Schrijver <pdeschrijver@...dia.com>
To:     Stephen Boyd <sboyd@...eaurora.org>
CC:     Prashant Gaikwad <pgaikwad@...dia.com>,
        Michael Turquette <mturquette@...libre.com>,
        Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        <linux-clk@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable

On Fri, Apr 21, 2017 at 07:38:48PM -0700, Stephen Boyd wrote:
> On 04/20, Peter De Schrijver wrote:
> > PLL SS was only controlled when setting the PLL rate, not when the PLL
> > itself is enabled or disabled. This means that if the PLL rate was set
> > before the PLL is enabled, SS will not be enabled, even when configured.
> > 
> > Signed-off-by: Peter De Schrijver <pdeschrijver@...dia.com>
> 
> Fixes tag? Or this isn't a problem right now, just future fix?
> 

This isn't a problem right now, at least noone complained about it.

Peter.