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Message-ID: <alpine.DEB.2.20.1705101551260.1979@nanos>
Date: Wed, 10 May 2017 15:56:51 +0200 (CEST)
From: Thomas Gleixner <tglx@...utronix.de>
To: "Liang, Kan" <kan.liang@...el.com>
cc: "'peterz@...radead.org'" <peterz@...radead.org>,
"'mingo@...hat.com'" <mingo@...hat.com>,
"'linux-kernel@...r.kernel.org'" <linux-kernel@...r.kernel.org>,
"'bp@...en8.de'" <bp@...en8.de>,
"'acme@...nel.org'" <acme@...nel.org>,
"'eranian@...gle.com'" <eranian@...gle.com>,
"'jolsa@...nel.org'" <jolsa@...nel.org>,
"'ak@...ux.intel.com'" <ak@...ux.intel.com>
Subject: RE: [PATCH V5] perf/x86: add sysfs entry to freeze counter on SMI
On Mon, 8 May 2017, Liang, Kan wrote:
> Hi tglx,
>
> Are you OK with patch?
> Could I get your "acked-by"?
No.
> > > +static void flip_smm_bit(void *data)
> > > +{
> > > + bool set = *(int *)data;
data points to an unsigned long. So while this works on LE machines this is
still crap.
> > > + if (set) {
> > > + msr_set_bit(MSR_IA32_DEBUGCTLMSR,
> > > + DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
> > > + } else {
> > > + msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
> > > + DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
> > > + }
I probably forgot, but why do we need an open coded version of __flip_bit()
instead of reusing that?
Thanks,
tglx
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